Samsung Electronics
7-3
Schematic Diagram
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7-2 Power Management
LED+
EXT_PWR
CPU_RST
CHG_STATUS
JTAG_RST
V_DDCON
INN_BATT P3.2V
P5V
P1.8V
P5V
P3.2V
P1.07V
V_DDCON
P3.2V
R
3
3
7
5
.6
K
R
3
0
5
1
8
K
R
3
3
8
1
0
K
R
3
1
3
1
0
0
K
R
3
0
4
2
2
K
R
3
3
5
1
0
0
K
R
3
3
2
1
K
R333
1K
R334
1K
R
3
1
8
1
2
0
K
GND
GND
GND
GND
GND
L
3
0
4
4
.7
u
H
L305
4.7uH
LED-
CHRG_CTL
POWER_OFF
RTC_INT
CHARGE_STOP
CPU_RST
PWR_IN_DDCON
C
3
0
9
0
.1
n
F
C
3
0
8
0
.1
n
F
C314
4700nF
C
3
2
8
1
0
0
0
n
F
C
3
3
0
1
0
0
n
F
1
6
V
C
3
2
6
0
.1
n
F
C
3
2
5
1
0
0
0
0
n
F
C
3
1
7
0
.1
n
F
C
3
1
0
2
2
n
F
C
3
1
1
4
7
0
0
n
F
Q307
KRC408V
D301
KDS121V
V
A
R
3
0
0
N
.C
V_DDCON
L301
4.7uH
C
3
0
0
4
7
0
0
n
F
5V_SPK_CTL
GND
SPK_5V
S
/W
3
0
0
1
2
V
C312
10uF
25V
GND
C
3
1
9
1
0
0
0
n
F
1
0
V
R310
0
R
3
0
6
0
R315
0
L
3
0
3
4
.7
u
H
P3.2V
R
3
2
8
2
2
0
K
GND
INN_BATT
CORE_VOLT2
CORE_VOLT1
LED_DIMMING
R
3
2
9
4
.7
K
R
3
3
0
1
0
0
K
GND
Q302
KRC408V
R
3
1
4
3
3
0
K
P3.2V
Q300
KRC408V
C
3
0
1
1
0
0
n
F
BATT_LEV
R
3
0
1
1
0
0
K
GND
INN_BATT
Q304
KRA304V
L300
60
R
3
0
8
4
7
K
D300
KDS121V
C
3
2
9
1
0
u
F
6
.3
V
C
3
0
2
1
0
u
F
1
0
V
R
3
3
1
3
.3
K
D303
RB551V-30
C
3
0
3
1
0
0
n
F
C
3
0
6
1
0
0
n
F
C
3
3
1
1
0
0
n
F
C
3
1
3
1
0
0
n
F
C
3
2
2
1
0
0
n
F
C
3
2
4
1
0
0
n
F
C
3
2
0
1
0
0
n
F
R
3
3
6
1
0
K
R
3
1
2
1
0
K
R
3
0
0
1
0
K
R
3
0
9
1
0
K
R
3
1
7
1
0
K
R324
10K
R
3
2
6
1
0
K
C
3
3
2
1
0
u
F
6
.3
V
C
3
2
7
1
0
u
F
6
.3
V
R
3
1
1
1
0
0
K
R
3
4
2
1
5
0
K
R
3
2
2
2
7
0
K
R
3
2
3
1
M
L306
10uH
R327
6.8K
R
3
2
1
5
1
K
R
3
1
9
1
5
0
K
Q301
KRC857E
1
2
3
4
5
6
IC302
7WH74
1
CK
2
D
3
Q
4
GND
5 Q
6 CLR
7 PR
8 VCC
IC304
MAX8819
1
C
O
M
P
4
2
F
B
4
3
O
V
P
4
4
P
G
4
5
L
X
4
6
G
N
D
7
E
N
4
15
C
H
G
16
P
G
1
17
L
X
1
18
P
V
1
3
19
L
X
3
20
P
G
3
21
D
L
IM
1
22
FB2
23
FB3
24
EN123
25
PV2
26
LX2
27
PG2
28
DLIM2
12
CEN
10
SYS
8
RST1
13
FB1
11
DC
9
BAT
14
CISET
Q303
KRC857E
1
2
3
4
5
6
C
3
3
3
1
0
u
F
6
.3
V
C
3
3
4
1
0
u
F
6
.3
V
IC300
AAT1265IJS-5.0-T1
1 1
2 2
3 3
4 4
5
5
6
6
7
7
8
8
C
3
1
6
1
0
u
F
1
6
V
C
3
1
8
1
0
u
F
1
6
V
LIM1
0
0
1
1
1% OK
1% OK
A
D
T
->
1
.8
V
3.0V
1% OK!
1% OK!
Charge(mA)
300mA
440mA
1% OK!
1% OK!
1% OK
1% OK
1% OK
R1
R2
3.3K X
3.3K
200ms delay
1% OK
6.8K
400mA
300mA
200mA
H
clear
PR
preset
ª
x
x
L
H
H
x
G ower off
H
/
Q
L
H
G ower on
L
ª CnI
H
H
Q
L
H
L
H
H
CLR
x
H
D
L
x
x
L
x
CK
H
1% OK
1% OK
1% OK
1% OK
Location Near CPU
0
1000mA
DC LIM(mA)
1
suspend
LIM2
1
95mA
0
475mA
(1
ª K
Default 1000mA set
~Rª M )
1% ª¶
POWER
TP3
TP4
TP2 / TP3 / TP4
TP3
TP2
TP2
TP4
Summary of Contents for YP-P3
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