Block Diagrams
7-2
Samsung Electronics
This Document can not be used without Samsung’s authorization
Head
Amp
CPU
ADC45
ADC225
ATF
GAIN
Control
Loop Filter
(Gain)
Loop Filter
(Timing)
Viterbi
DAC225
DAC45
ATFout
TEST_analog
PB_CLK
PB_DATA
NCO
PLL/VCO
System Clock
(45MHz)
Function Control
Function Control
Fix
Filter
Interpolator
BPF
HPF
APF
Serial Control
Register
Error
Detection
5TAP
FIR
Blind
Control
refCLK
To
DV Decoder
<Coefficient>
8
8
8
8
7-2 IC102 Block Diagram
