Samsung SF700AT, Service Manual

Page: 25 / 64

Circuit Description
SF700AT 5-7
Figure 5-10: CIS Driver Clock Timing
5-2-10 CIS Driver
The CIS driver clock frequency is 500 kHz. A low
duty cycle of 50% is used to lengthen the charging
time. A start signal is provided every 5 ms to
match the line scanning time. Actual image signal
is provided in less than 4.1 ms, using the 500 kHz
clock and taking B4 paper size into consideration.
500 KHZ (L:DUTY 50 %)
SI
CLOCK
SIG
1 LINE
Figure 5-9: Scanner Interface Block Diagram
5-2-9 CIS Input Processor
To process the B/W input signal, maximum
(+V
REF
) and minimum (-V
REF
) values of the CIS
input signal are controlled by calibrating MUXA
and MUXB in the high state for the maximum
level, and setting them to earth for the minimum
level.
Processing to compensate for CIS shading
distortion is controlled with MUXA 'low' and
MUXB 'high'. For B/W mode, MUXA should be
'high', and MUXB 'low'. For half-tone, MUXA is
'low', and MUXB is 'high'.
XFC-B External Circuits
Dither & Shading
Correction
Tables
Scanner Image
Processing
Shading RAM
External
RAM
Line Buffer
RAM
6-bit FADC
Video
Processing
-Vref
+Vref
+
-
Vin
Scanner
VIDCTL(1:0)
Drivers
Start, CLK1.
CLK1n, CLK2
Scanner
Timing & Control
CPUCLK