Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-31
4.8 INTERNAL MEMORY CONTROL
Table 4-9
shows the internal memory power control summary.
Table 4-9 S5PC110 Internal Memory Control
Block Controlled by NORMAL
IDLE/
DEEP-IDLE
(1)
DEEP-IDLE
(2)
/ STOP /
DEEP-STOP
SLEEP
1 SRAM SYSCON
Run /
Stand-by
Keep operation
or power state
in NORMAL
Stand-by
Retention /
Power-down
(Power off)
2 ROM SYSCON
Run /
Stand-by /
Power-down
Keep operation
or power state
in NORMAL
Stand-by /
Power-down
(Power off)
4.8.1 SRAM
SRAM in TOP block has four power modes, namely, Run, Stand-by, Retention, and Power-down mode.
•
In Run mode, read and write access to SRAM can be performed normally.
•
In Stand-by mode, SRAM chip select is deactivated, so that there is no read and write access.
•
In Retention mode, power is provided to only core of SRAM, and power to peripheral circuitry is ”OFF”
internally.
•
In Power-down mode, all power to core and peripheral circuitry is ”OFF”.
In NORMAL mode, run, or stand-by mode can be used.
Run mode is used when there is read and write access, while stand-by mode is used when there is no read and
write access. The change between these two modes can be done by module that has SRAM.
In IDLE mode, and DEEP-IDLE mode where TOP block is ”ON”, SRAM keeps its operation or power state in
NORMAL.
In DEEP-IDLE mode where TOP block is ”OFF”, SRAM in TOP module can enter stand-by, retention, or power-
down mode. Before entering this mode, you must set the TOP_MEMORY field IDLE_CFG in SYSCON.
In STOP mode and DEEP-STOP mode, stand-by, retention, and power-down mode can be entered.
Before entry to STOP mode, you must set the TOP_MEMORY field of STOP_CFG register in SYSCON to
determine which power mode SRAM will enter during STOP mode.
In SLEEP mode, power to SRAM is off, so the data in SRAM will be lost. Power mode in SLEEP mode has no
meaning.