Samsung S5PC110, Manual

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S5PC110_UM 4 POWER MANAGEMENT
4-1
4
POWER MANAGEMENT
This chapter describes the Power Management Unit (PMU) in S5PC110. SYSCON manages clock management
unit (CMU) and PMU in S5PC110.
4.1 OVERVIEW OF PMU
Mobile application processors such as the S5PC110 should consume less power, since mobile products have a
small battery with limited power capacity. The purpose of PMU is to provide various methods in S5PC110 to
consume less power under specific application scenarios.
The power management scheme in S5PC110 provides six system power modes, namely,
Normal, Idle, Deep-idle,
Stop, Deep-stop,
and
Sleep
modes.
The description of each power mode is given as follows:
•
Normal
: In this mode, the CPU core is running, that is, the software is running.
•
Idle
: In this mode, the CPU core is idle, that is, the CPU core clock is disabled but the remaining parts of the
S5PC110 are running.
•
Deep-idle
: In this mode, the CPU core is power-gated, that is, the CPU core power is supplied, but is
powered off by the internal power switch. The remaining parts of the chip remain the same as those in the
Normal
mode, or become power-gated (except Audio power domain for application of low power MP3
playback).
•
Stop
: In this mode, the S5PC110 is clock-gated (except RTC module). Therefore, application programming
stops and waits for wakeup event to resume its operation. Also, the CPU core clock is disabled. (
Note
: The
power-gated block in
Normal
mode is still power-gated in
Stop
mode.)
•
Deep-stop
: In this mode, the CPU core and remaining parts of the chip are power-gated (except TOP, RTC,
and ALIVE modules). The TOP module can be power-gated or powered-on.
•
Sleep
: In this mode, the internal power (1.1V) of the S5PC110 is externally turned off using regulator or power
management IC (PMIC). Therefore, the internal power to S5PC110 is powered “off” except ALIVE block.
(
Note
: RTC power to RTC and external power to I/O pad is still "on". If wakeup event occurs, S5PC110 is
initialized by wakeup reset, as though power-on reset was asserted.)
‘
Deep
’ means CPU core is power-gated. Therefore, leakage power of CPU core is minimized in
Deep-idle
and
Deep-stop
power modes.
The above description about power mode is given in view of internal digital logic. For more information on non-
digital logic, refer to
4.5 "Cortex-A8 Power Mode"
,
4.7 "External Power Control"
, and
4.8 "Internal memory
control"
.
PMU controls the power mode of SRAM and PLL. However, the power mode of analog IP (except SRAM and
PLL) should be controlled by its corresponding control module.
In addition to the PMU, clock controller (CLKCON) also controls the PLL.