Samsung S3C8248, User Manual

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16-BIT TIMER 0/1 S3C8248/C8245/P8245/C8247/C8249/P8249
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FUNCTION DESCRIPTION
Timer 1 Interrupts (IRQ3, Vectors E8H and EAH)
The timer 1 module can generate two interrupts, the timer 1 overflow interrupt (T1OVF), and the timer 1
match/capture interrupt (T1INT). T1OVF is interrupt level IRQ3, vector EAH. T1INT also belongs to interrupt
level IRQ3, but is assigned the separate vector address, E8H.
A timer 1 overflow interrupt pending condition is automatically cleared by hardware when it has been serviced.
A timer 1 match/capture interrupt, T1INT pending condition is also cleared by hardware when it has been
serviced.
Interval Timer Function
The timer 1 module can generate an interrupt: the timer 1 match interrupt (T1INT). T1INT belongs to interrupt
level IRQ3, and is assigned the separate vector address, E8H. When a timer 1 measure interrupt occurs and is
serviced by the CPU, the pending condition is cleared automatically by hardware.
In interval timer mode, a match signal is generated and T1OUT is toggled when the counter value is identical to
the value written to the T1 reference data register, T1DATAH/L. The match signal generates a timer 1 match
interrupt (T1INT, vector E8H) and clears the counter.
If, for example, you write the value 0010H to T1DATAH/L and 06H to T1CON, the counter will increment until it
reaches 0010H. At this point, the T1 interrupt request is generated, the counter value is reset, and counting
resumes.
Pulse Width Modulation Mode
Pulse width modulation (PWM) mode lets you program the width (duration) of the pulse that is output at the
T1PWM pin. As in interval timer mode, a match signal is generated when the counter value is identical to the
value written to the timer 1 data register. In PWM mode, however, the match signal does not clear the counter
but can generate a match interrupt. The counter runs continuously, overflowing at FFFFH, and then repeat the
incrementing from 0000H. Whenever an overflow is occurred, an overflow (OVF) interrupt can be generated.
Although you can use the match or the overflow interrupt in PWM mode, interrupts are not typically used in
PWM-type applications. Instead, the pulse at the T1PWM pin is held to Low level as long as the reference data
value is less than or equal to (
≤
) the counter value and then pulse is held to High level for as long as the data
value is greater than (>) the counter value. One pulse width is equal to t
CLK
Capture Mode
In capture mode, a signal edge that is detected at the T1CAP pin opens a gate and loads the current counter
value into the T1 data register. You can select rising or falling edges to trigger this operation.
Timer 1 also gives you capture input source, the signal edge at the T1CAP pin. You select the capture input by
setting the value of the timer 1 capture input selection bit in the port 1 control register low, P1CONL, (set 1 bank
0, E5H). When P1CONL.1.0 is 00, the T1CAP input or normal input is selected .When P1CONL.1.0 is set to 11,
normal output is selected.
Both kinds of timer 1 interrupts can be used in capture mode, the timer 1 overflow interrupt is generated
whenever a counter overflow occurs, the timer 1 match/capture interrupt is generated whenever the counter
value is loaded into the T1 data register.
By reading the captured data value in T1DATAH/L, and assuming a specific value for the timer 1 clock
frequency, you can calculate the pulse width (duration) of the signal that is being input at the T1CAP pin.