Samsung
Confidential
MPLL
DPLLB
Disable
ICH7-M
USBPLL
SATAPLL
32.768 KHz
33 MHz
667/533/400 MHz
CLK1_MCLK3/3*
CLK1_MCLK2/2*
CLK1_MCLK0/0*
CLK1_MCLK1/1*
HD 24 MHz
AUD3_BCLK
33 MHz CLK3_PCLKMICOM
BSEL
14 MHz
OSC
Main PLL
CPU
100 MHz
CLK1_DREFCLK/CLK*
CPU
GMCH
EXPRESS CARD
SODIMM #0
14.318 MHz
CK-410M (w/ CLKREQ*)
ICS954305D
10 MHz
OPTION
Page 8
SODIMM #1
MCH3_CLKREQ*
CLK1_PEG/PEG*
CLK1_EXPCARD/CARD*
EXP3_CLKREQ*
CLK1_MINIPCIE/PCIE*
100 MHz
MPCIE3_CLKREQ*
HPLL
3GPLL
DPLLA
100 MHz
100 MHz
GIGA on DOCK
CLK1_DCKPCIELAN/LAN*
100 MHz
100 MHz
FWH
PCIEPLL
Calistoga
PCI Express Gfx
100 MHz
333/266/200 MHz
333/266/200 MHz
166 MHz
CLK0_HOST_CPU/CPU*
166 MHz
CLK0_HOST_GMCH/GMCH*
CLK1_DREFSSC/SSC*
100 MHz
CLK1_MCH3GPLL/3GPLL*
100 MHz
CLK3_USB48
48 MHz
CLK1_SATA/SATA*
100 MHz
CLK3_ICH14
14.318 MHz
CHP3_SATACLKREQ*
CLK3_PCLKICH
33 MHz
2
SAMSUNG ELECTRONICS CO’S PROPERTY.
SAMSUNG PROPRIETARY
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
PROPRIETARY INFORMATION THAT IS
DEV. STEP
C
48MHz PLL
96/100 MHz
SSCD
33 MHz
Buffer
MUX
MUX
MUX
SATA PLL
FSB
96 MHz
CLK1_PCIEICH/ICH*
100 MHz
CLK1_PCIELOM/LOM*
MDC3_BCLK
32.768 KHz
RTC Clock
CLK_3.3V
CLK3_PWRGD*
MCLK2/2* & MCLK3/3* swapped for ease of routing.
100 MHz
100 MHz
100 MHz
C
EXCEPT AS AUTHORIZED BY SAMSUNG.
DATE
PART NO.
TITLE
B
D
LAN
MICOM
DEBUG
OPTION
33 MHz
CLK3_PCLKFWH
CLK3_PCLKLAN
CLK3_DBGLPC
4
LAST EDIT
4
REV
3
CHECK
333/266/200 MHz
333/266/200 MHz
OSC
HD Audio
MDC
MINI PCIE CARD
GIGA LAN
A
1
DRAW
1
APPROVAL
PAGE
OF
2
SAMSUNG
MODULE CODE
D
ELECTRONICS
THIS DOCUMENT CONTAINS CONFIDENTIAL
B
A
3
CLOCK DIAGRAM
SHANGHAI
54
6
BA41-00774A/00732A
March 15, 2007 10:33:33 AM
1.0
SR
3/15/2007
LEE, KEVIN
ZHENG, ROKY
ZHANG, ELLEN
PEG
DMI
FS(2:0)
CPU_STP*
ITP_EN
SS(96/100) SEL
PCI_STP*
