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Samsung M471B1G73AH0, Hardware User Manual

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Samsung M471B1G73AH0 Hardware User Manual Download Page 5

- 5 -

Unbuffered SODIMM

datasheet

DDR3 SDRAM

Rev. 1.0

4. x64 DIMM Pin Configurations (Front side/Back Side)

NOTE

 :

1. NC = No Connect, NU = Not Used, RFU = Reserved Future Use
2. TEST(pin 125) is reserved for bus analysis probes and is NC on normal memory modules.
3. This address might be connected to NC balls of the DRAMs (depending on density); either way they will be connected to the termination resistor.

SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.

Pin

Front

Pin

Back

Pin

Front

Pin

Back

Pin

Front

Pin

Back

1

V

REFDQ

2

V

SS

71

V

SS

72

V

SS

139

V

SS

140

DQ38

3

V

SS

4

DQ4

KEY

141

DQ34

142

DQ39

5

DQ0

6

DQ5

73

CKE0

74

CKE1

143

DQ35

144

V

SS

7

DQ1

8

V

SS

75

V

DD

76

V

DD

145

V

SS

146

DQ44

9

V

SS

10

DQS0

77

NC

78

A15

3

147

DQ40

148

DQ45

11

DM0

12

DQS0

79

BA2

80

A14

3

149

DQ41

150

V

SS

13

V

SS

14

V

SS

81

V

DD

82

V

DD

151

V

SS

152

DQS5

15

DQ2

16

DQ6

83

A12/BC

84

A11

153

DM5

154

DQS5

17

DQ3

18

DQ7

85

A9

86

A7

155

V

SS

156

V

SS

19

V

SS

20

V

SS

87

V

DD

88

V

DD

157

DQ42

158

DQ46

21

DQ8

22

DQ12

89

A8

90

A6

159

DQ43

160

DQ47

23

DQ9

24

DQ13

91

A5

92

A4

161

V

SS

162

V

SS

25

V

SS

26

V

SS

93

V

DD

94

V

DD

163

DQ48

164

DQ52

27

DQS1

28

DM1

95

A3

96

A2

165

DQ49

166

DQ53

29

DQS1

30

RESET

97

A1

98

A0

167

V

SS

168

V

SS

31

V

SS

32

V

SS

99

V

DD

100

V

DD

169

DQS6

170

DM6

33

DQ10

34

DQ14

101

CK0

102

CK1

171

DQS6

172

V

SS

35

DQ11

36

DQ15

103

CK0

104

CK1

173

V

SS

174

DQ54

37

V

SS

38

V

SS

105

V

DD

106

V

DD

175

DQ50

176

DQ55

39

DQ16

40

DQ20

107

A10/AP

108

BA1

177

DQ51

178

V

SS

41

DQ17

42

DQ21

109

BA0

110

RAS

179

V

SS

180

DQ60

43

V

SS

44

V

SS

111

V

DD

112

V

DD

181

DQ56

182

DQ61

45

DQS2

46

DM2

113

WE

114

S0

183

DQ57

184

V

SS

47

DQS2

48

V

SS

115

CAS

116

ODT0

185

V

SS

186

DQS7

49

V

SS

50

DQ22

117

V

DD

118

V

DD

187

DM7

188

DQS7

51

DQ18

52

DQ23

119

A13

3

120

ODT1

189

V

SS

190

V

SS

53

DQ19

54

V

SS

121

S1

122

NC

191

DQ58

192

DQ62

55

V

SS

56

DQ28

123

V

DD

124

V

DD

193

DQ59

194

DQ63

57

DQ24

58

DQ29

125

TEST

126

V

REFCA

195

V

SS

196

V

SS

59

DQ25

60

V

SS

127

V

SS

128

V

SS

197

SA0

198

NC

61

V

SS

62

DQS3

129

DQ32

130

DQ36

199

V

DDSPD

200

SDA

63

DM3

64

DQS3

131

DQ33

132

DQ37

201

SA1

202

SCL

65

V

SS

66

V

SS

133

V

SS

134

V

SS

203

V

TT

204

V

TT

67

DQ26

68

DQ30

135

DQS4

136

DM4

69

DQ27

70

DQ31

137

DQS4

138

V

SS

Summary of Contents for M471B1G73AH0

Page 1: ...ty to the other party under this document by implication estoppel or other wise Samsung products are not intended for use in life support critical care medical safety equipment or similar applications where product failure could result in loss of life or personal or physical harm or any military or defense application or any governmental procurement to which special terms or provisions may apply F...

Page 2: ... 2 Unbuffered SODIMM datasheet DDR3 SDRAM Rev 1 0 Revision History Revision No History Draft Date Remark Editor 1 0 First Release Jul 2010 S H Kim ...

Page 3: ... Swing Requirement for Clock CK CK and Strobe DQS DQS 12 10 3 3 Single ended Requirements for Differential Signals 13 10 3 4 Differential Input Cross Point Voltage 14 10 4 Slew Rate Definition for Single Ended Input Signals 14 10 5 Slew rate definition for Differential Input Signals 14 11 AC DC Output Measurement Levels 15 11 1 Single Ended AC and DC Output Levels 15 11 2 Differential AC and DC Ou...

Page 4: ...limit sequential with starting address 000 only 4 with tCCD 4 which does not allow seamless read or write either On the fly using A12 or MRS Bi directional Differential Data Strobe On Die Termination using ODT pin Average Refresh Period 7 8us at lower then TCASE 85 C 3 9us at 85 C TCASE 95 C Asynchronous Reset 3 Address Configuration Part Number2 Density Organization Component Composition Number o...

Page 5: ...2 158 DQ46 21 DQ8 22 DQ12 89 A8 90 A6 159 DQ43 160 DQ47 23 DQ9 24 DQ13 91 A5 92 A4 161 VSS 162 VSS 25 VSS 26 VSS 93 VDD 94 VDD 163 DQ48 164 DQ52 27 DQS1 28 DM1 95 A3 96 A2 165 DQ49 166 DQ53 29 DQS1 30 RESET 97 A1 98 A0 167 VSS 168 VSS 31 VSS 32 VSS 99 VDD 100 VDD 169 DQS6 170 DM6 33 DQ10 34 DQ14 101 CK0 102 CK1 171 DQS6 172 VSS 35 DQ11 36 DQ15 103 CK0 104 CK1 173 VSS 174 DQ54 37 VSS 38 VSS 105 VDD...

Page 6: ...trobe 1 DQS0 DQS7 Data strobes complement 8 CAS Column Address Strobe 1 RESET Reset Pin 1 WE Write Enable 1 TEST Logic Analyzer specific test pin No connect on SODIMM 1 S0 S1 Chip Selects 2 VDD Core and I O Power 18 A0 A9 A11 A13 A15 Address Inputs 14 VSS Ground 52 A10 AP Address Input Autoprecharge 1 VREFDQ VREFCA Input Output Reference 2 A12 BC Address Input Burst chop 1 VDDSPD SPD and Temp sens...

Page 7: ...d and BA0 BAn defines the bank to be precharged If AP is low autoprecharge is disabled During a Precharge command cycle AP is used in conjunction with BA0 BAn to control which bank s to precharge If AP is high all banks will be pre charged regardless of the state of BA0 BAn inputs If AP is low then BA0 BAn are used to define which bank to pre charge A12 BC is sampled during READ and WRITE commands...

Page 8: ...WE CK CK CKE ODT A N 0 BA N 0 ZQ DQ 0 7 DM 240Ω 1 DQ 0 7 D8 CS RAS CAS WE CK CK CKE ODT A N 0 BA N 0 ZQ 240Ω 1 DQS DQS DQ 0 7 DM DQS2 DQS2 DM2 DQS DQS D2 CS RAS CAS WE CK CK CKE ODT A N 0 BA N 0 ZQ DQ 0 7 DM 240Ω 1 DQ 16 23 D10 CS RAS CAS WE CK CK CKE ODT A N 0 BA N 0 ZQ 240Ω 1 DQS DQS DQ 0 7 DM DQS DQS D4 CS RAS CAS WE CK CK CKE ODT A N 0 BA N 0 ZQ DQ 0 7 DM 240Ω 1 D12 CS RAS CAS WE CK CK CKE ODT...

Page 9: ...under all operating conditions 3 Some applications require operation of the Extended Temperature Range between 85 C and 95 C case temperature Full specifications are guaranteed in this range but the following additional conditions apply a Refresh commands must be doubled in frequency therefore reducing the refresh interval tREFI to 3 9us It is also possible to specify a component with 1X refresh t...

Page 10: ... 2 15mV 5 VIH dc is used as a simplified symbol for VIH DQ DC100 6 VIL dc is used as a simplified symbol for VIL DQ DC100 7 VIH ac is used as a simplified symbol for VIH DQ AC175 VIH DQ AC150 VIH DQ AC175 value is used when VREF 175mV is referenced VIH DQ AC150 value is used when VREF 150mV is referenced 8 VIL ac is used as a simplified symbol for VIL DQ AC175 VIL DQ AC150 VIL DQ AC175 value is us...

Page 11: ... levels for setup and hold time measurements VIH AC VIH DC VIL AC and VIL DC are dependent on VREF VREF shall be understood as VREF DC as defined in Figure 1 This clarifies that dc variations of VREF affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured System timing and voltage budgets need to account for ...

Page 12: ...the respective limits VIH DC max VIL DC min for single ended sig nals as well as the limitations for overshoot and undershoot Refer to overshoot and Undershoot Specification Table 3 Allowed time before ringback tDVAC for CK CK and DQS DQS Symbol Parameter DDR3 800 1066 1333 1600 unit NOTE min max VIHdiff differential input high 0 2 NOTE 3 V 1 VILdiff differential input low NOTE 3 0 2 V 1 VIHdiff A...

Page 13: ...ingle ended signals through the ac levels is used to measure setup time For single ended components of differential signals the requirement to reach VSELmax VSEHmin has no bearing on timing but adds a restriction on the common mode characteristics of these signals Table 4 Single ended levels for CK DQS CK DQS NOTE 1 For CK CK use VIH VIL AC of ADD CMD for strobes DQS DQS use VIH VIL AC of DQs 2 VI...

Page 14: ...lew rate definitions for address and command signals See Data Setup Hold and Slew Rate Derating for single ended slew rate definitions for data signals 10 5 Slew rate definition for Differential Input Signals Input slew rate for differential signals CK CK and DQS DQS are defined and measured as shown in below Table 6 Differential input slew rate definition NOTE The differential signal i e CK CK an...

Page 15: ...ded output slew rate Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output se Single ended Signals For Ron RZQ 7 setting Figure 6 Single ended output slew rate definition Symbol Parameter DDR3 800 1066 1333 1600 Units NOTE VOH DC DC output high measurement level for IV curve linearity 0 8 x VDDQ V VOM DC DC output mid measurement level for IV curve linearity 0 5 ...

Page 16: ...l Output slew rate Description SR Slew Rate Q Query Output like in DQ which stands for Data in Query Output diff Differential Signals For Ron RZQ 7 setting Figure 7 Differential output slew rate definition Description Measured Defined by From To Differential output slew rate for rising edge VOLdiff AC VOHdiff AC VOHdiff AC VOLdiff AC Delta TRdiff Differential output slew rate for falling edge VOHd...

Page 17: ...1 AL 0 CS stable at 1 Command Address Bank Address Inputs stable at 0 Data IO FLOATING DM stable at 0 Bank Activity all banks open Output Buffer and RTT Enabled in Mode Registers2 ODT Signal stable at 0 IDD4R Operating Burst Read Current CKE High External clock On tCK CL Refer to Component Datasheet for detail pattern BL 81 AL 0 CS High between RD Command Address Bank Address Inputs partially togg...

Page 18: ...4 Auto Self Refresh ASR set MR2 A6 0B to disable or 1B to enable feature 5 Self Refresh Temperature Range SRT set MR2 A7 0B for normal or 1B for extended temperature range 6 Refer to DRAM supplier data sheet and or DIMM SPD to determine if optional features or requirements are supported by DDR3 SDRAM device 7 IDD current measure method and detail patterns are described on DDR3 component datasheet ...

Page 19: ...actived rank IDLE is IDD2N Symbol CF8 DDR3 1066 CL 7 CH9 DDR3 1333 CL 9 Unit NOTE IDD0 600 680 mA 1 IDD1 720 800 mA 1 IDD2P0 slow exit 240 240 mA IDD2P1 fast exit 320 320 mA IDD2N 400 480 mA IDD2Q 400 400 mA IDD3P 400 400 mA IDD3N 520 600 mA IDD4R 960 1120 mA 1 IDD4W 1040 1280 mA 1 IDD5B 1440 1600 mA 1 IDD6 240 240 mA IDD7 1520 1880 mA 1 IDD8 240 240 mA ...

Page 20: ...acitance 14 1 2Rx8 2GB SODIMM Parameter Symbol M471B1G73AH0 Units NOTE DDR3 1066 DDR3 1333 Min Max Min Max Input output capacitance DQ DM DQS DQS TDQS TDQS CIO TBD TBD pF Input capacitance CK and CK CCK TBD TBD pF Input capacitance All other input only pins CI TBD TBD pF ...

Page 21: ...o active refresh cmd time tRFC 110 160 300 350 ns Average periodic refresh interval tREFI 0 C TCASE 85 C 7 8 7 8 7 8 7 8 μs 85 C TCASE 95 C 3 9 3 9 3 9 3 9 μs 1 Speed DDR3 800 DDR3 1066 DDR3 1333 DDR3 1600 Units NOTE Bin CL tRCD tRP 6 6 6 7 7 7 9 9 9 11 11 11 Parameter min min min min CL 6 7 9 11 tCK tRCD 15 13 13 13 5 13 75 ns tRP 15 13 13 13 5 13 75 ns tRAS 37 5 37 5 36 35 ns tRC 52 5 50 63 49 5...

Page 22: ...ommand period tRP 13 125 ns ACT to ACT or REF command period tRC 50 625 ns ACT to PRE command period tRAS 37 5 9 tREFI ns CL 5 CWL 5 tCK AVG 3 0 3 3 ns 1 2 3 4 5 9 10 CWL 6 tCK AVG Reserved ns 4 CL 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 5 CWL 6 tCK AVG Reserved ns 1 2 3 4 CL 7 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 8 CL 8 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2...

Page 23: ... 9 tREFI ns CL 5 CWL 5 tCK AVG 3 0 3 3 ns 1 2 3 4 6 9 10 CWL 6 7 tCK AVG Reserved ns 4 CL 6 CWL 5 tCK AVG 2 5 3 3 ns 1 2 3 6 CWL 6 tCK AVG Reserved ns 1 2 3 4 6 CWL 7 tCK AVG Reserved ns 4 CL 7 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 6 CWL 7 tCK AVG Reserved ns 1 2 3 4 CL 8 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 6 CWL 7 tCK AVG Reserved ns 1 2 3 4 CL 9 ...

Page 24: ... 2 5 3 3 ns 1 2 3 7 CWL 6 tCK AVG Reserved ns 1 2 3 4 7 CWL 7 8 tCK AVG Reserved ns 4 CL 7 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 4 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 7 CWL 8 tCK AVG Reserved ns 4 CL 8 CWL 5 tCK AVG Reserved ns 4 CWL 6 tCK AVG 1 875 2 5 ns 1 2 3 7 CWL 7 tCK AVG Reserved ns 1 2 3 4 7 CWL 8 tCK AVG Reserved ns 1 2 3 4 CL 9 CWL 5 6 tCK AVG Reserved ns 4 CWL 7 t...

Page 25: ...subject to Production Tests but verified by Design Characterization 6 Any DDR3 1333 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests but verified by Design Characterization 7 Any DDR3 1600 speed bin also supports functional operation at lower frequencies as shown in the table which are not subject to Production Tests ...

Page 26: ... across n 13 14 49 50 cycles tERR nper tERR nper min 1 0 68ln n tJIT per min tERR nper max 1 0 68ln n tJIT per max ps 24 Absolute clock HIGH pulse width tCH abs 0 43 0 43 0 43 0 43 tCK avg 25 Absolute clock Low pulse width tCL abs 0 43 0 43 0 43 0 43 tCK avg 26 Data Timing DQS DQS to DQ skew per group per access tDQSQ 200 150 125 100 ps 13 DQ output hold time from DQS DQS tQH 0 38 0 38 0 38 0 38 t...

Page 27: ...page size tFAW 40 37 5 30 30 ns e Four activate window for 2KB page size tFAW 50 50 45 40 ns e Command and Address setup time to CK CK referenced to VIH AC VIL AC levels tIS base AC175 200 125 65 45 ps b 16 tIS base AC150 200 150 125 150 65 125 45 125 ps b 16 27 Command and Address hold time from CK CK refer enced to VIH AC VIL AC levels tIH base DC100 275 200 140 120 ps b 16 Control Address Input...

Page 28: ...CK 10 Timing of WR command to Power Down entry BC4MRS tWRPDEN WL 2 tWR tCK avg WL 2 tWR tCK avg WL 2 tWR tCK avg WL 2 tWR tCK avg nCK 9 Timing of WRA command to Power Down entry BC4MRS tWRAPDEN WL 2 WR 1 WL 2 WR 1 WL 2 WR 1 WL 2 WR 1 nCK 10 Timing of REF command to Power Down entry tREFPDEN 1 1 1 1 20 21 Timing of MRS command to Power Down entry tMRSPDEN tMOD min tMOD min tMOD min tMOD min ODT Tim...

Page 29: ...e the device will support tnRP RU tRP tCK avg which is in clock cycles if all input clock jitter specifications are met This means For DDR3 800 6 6 6 of which tRP 15ns the device will support tnRP RU tRP tCK avg 6 as long as the input clock jitter specifications are met i e Precharge com mand at Tm and Active command at Tm 6 is valid even if Tm 6 Tm is less than 15ns due to input clock jitter Spec...

Page 30: ...ose operations 21 Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN min is satisfied there are cases where additional time such as tXPDLL min is also required See Device Operation Timing Diagram Datasheet 22 Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function 23 One ZQCS command can effectively correct a minimum of 0 5 ZQCorrect...

Page 31: ...DDR3 SDRAM FBGA DDR3 SDRAM Part NO K4B4G0846A HC NOTE Tolerances on all dimensions 0 15 unless otherwise specified 0 25 MAX 2 55 Detail B Detail A 1 00 0 10 0 45 0 03 4 00 0 10 0 10 A B M C 2X 4 00 0 10 0 10 A B M C 2X 1 80 OPTIONAL HOLES 0 60 Units Millimeters 21 00 24 80 63 60 39 00 A B Max 3 8 1 00 0 10 SPD 1 65 6 30 00 0 15 20 00 67 60 0 10 A B M C ...

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