Samsung DVD-907, Service Manual

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Circuit Descriptions
Samsung Electronics 7-19
Circuit Descriptions
7-18 Samsung Electronics
It measures the timing that data processed in DIC1 at DVD playback enters MUX(BIC8, BIC9)
• CH1 : SBGN (DICI-92, SECTOR BEGIN)
• CH2 : SDCK (DICI-94, CLOCK)
• CH3 : SREQ (DICI-96, DATA REQUEST)
• CH4 : SERR (DICI-91, DATA ERROR)
• CH5 : SDATA (DICI-81~84, 87~90, DATA)
Fig. 7-35
It shows the timing of control signal, address and data bus when micom accesses DIC1.
So to speak, timing at writing a value in the internal register of DIC1.
• CH1 : DPCS (DIC1-12, TC90A19F chip select)
• CH3 : WR (DIC1-10, TC90A19F register write)
• CH4 : RD (DIC1-11, TC90A19F register read)
• CH5 : HADRS (DIC1-24,25, Micom address bus)
• CH6 : HAD (DIC1-13~20, Micom data bus)
Fig. 7-36
It shows a waveform that DIC1 requests a management to micom by interrupt generation.
Micom recognizes the interrupt and writes a value in register of DIC1 to respond (instruction) for interrupt. Micom
accesses DIC1 five times in Figure. Micom recognizes the operation of chip and makes a necessary
instruction after receiving the interrupt generated in DIC1 and accessing the corresponding chip.
Fig. 7-37
• CH1 : DPCS (DIC1-12, TC90A19F chip select)
• CH2 : DPINT (DIC1-23, TC90A19F interrupt output)
• CH3 : WR (DIC1-10, TC90A19F register write)
• CH4 : RD (DIC1-11, TC90A19Fregister read)
• CH5 : HADRS (DIC1-24,25, Micom address bus)
• CH6 : HAD (DIC1-13~20, Micom data bus)
SBGN
SDCK
SREQ
SENB
SERR
SDATA
/DPCS
/WAIT
/WR
/RD
HADRS all
HAD all
/DPCS
/WAIT
/WR
/RD
HADRS all
HAD all
DIC1 shares the data bus of micom with other devices(A/V Decoder, EPROM, SRAM). CH2 shows the measure-
ment of a signal line of data bus. The inclining and rising part in CH2 indicates high impedence state after data bus
floating.The data bus is pulled up by 4.7K resistance.
• CH1 : ALE (MIC4-11, Address latch enable
signal)
• CH2 : HAD0-7 (MIC4-2 to 9, Main micom
address and data multiplexed bus)
• CH3 : HA0-7 (MIC4-19 to 12, Main micom
addreess 0-7)
Fig. 7-31
It shows access in fast page mode as waveform when DIC1 accesses external memory(4Mbit DRAM) at DVD
refresh.
• WE : Write enable(DIC2-7)
• OE : OUTPUT ENABLE (DIC2-22)
• RAS : RAW ADDRESS STROBE (DIC2-8)
• CAS : COLUMN ADDRESS STROBE (DIC2-23)
• ADRS : ADDRESS
• DATA : DATA
Fig. 7-32
It shows the external memory refresh of DIC1 and uses CAS Before RAS Refresh.
• DIC2 (4MDRAM) REFRESH TIME
Fig. 7-33
It shows refresh per approx. 31 usec as measurement of refresh waverform outputted by DIC1 in large timing.
Refresh time(Period) of DIC2(4MDRAM)
Fig. 7-34
1
2
3
WR
OE
RAS
ADRS
CAS
DATA
RAS
CAS
RAS
CAS