Samsung DVD-907, Service Manual

Page: 76 / 146

Circuit Descriptions
Samsung Electronics 7-17
Circuit Descriptions
7-16 Samsung Electronics
Because RF signal, external VCO input voltage and VCO control voltage swings terribly at disc halt, PLL ouput
clock changes largely.(PLL not unlock state)
• CH1 : RFIN(DIC1-50, RF Input signal at disc
halt)
• CH2 : VCO control signal (DD1-3, Variable
capacitance diode)
Fig. 7-28
The input voltage of VCO becomes a regular voltage level(approx. 3.59V in Figure) at DVD playback and VCO
outputs PLL clock depending on this control voltage. The input voltage of VCO swings a little and appears as
frequency variation of VCO as much as change amount. As the control voltage of VCO is higher, PLL clock
frequency becomes high.
• CH1 : RFIN(DIC1-50, RF Input signal at disc
playback)
• CH2 : VCO control signal (DD1-3, Variable
capacitance diode)
Fig. 7-29
After the error-correcting process of input RF signal in DIC1 it makes the acknowlegde signal of CH2 LOW and out-
puts data (CH4).
when MPEG decoder(Video, Audio signal process chip) falls the request signal to 0(LOW) and demands data. The
data acknowledge signal of CH2 and data of CH4 are synchronized with BSTCLK(CH3) and outputted. BSTCLK of
CH3 is made by division of 33MHz into 16.
• CH1 : PVSREQ (DIC1-96, Data request signal
from DVD1)
• CH2 : PVSACK (DIC1-93, Output data
acknowledge signal)
• CH3 : BSTCLK (DIC1-94, Output clock)
• CH4 : PVSIN (DIC1-81~84,87~90, Output data)
Fig. 7-30
1
2
2
1
1
2
3
4
A clock locked by PLL on the basis of input RF signal, PLL clock and trigger may be shown at DVD playback.
The eye of RF signal is open in PLL lock state.
• CH1 : RFIN(DIC1-50, RF Input signal)
(Vp-p is approx. 2.5V)
• CH4 : PLCK (DIC1-26, PLL clock)
Fig. 7-25
It shows RF signal and RLLD signal waveform at DVD refresh and RLLD waveform is regular as 1.65V. If a
serious error occurs in disc, RLLD signal is outputted as correction signal and enters PLL control system after
summing with phase difference signal.
• CH1 : RFIN(DIC1-50, RF Input signal)
• CH2 : RLLD (DIC1-38, RLLD signal at disk
refresh)
Fig. 7-26
RLLD signal is ouputted at disc halt or occurrence of serious error.
• CH1 : RFIN(DIC1-50, RF Input signal)
• CH2 : RLLD (DIC1-38, RLLD at disc halt or
occurrence of serious error)
Fig. 7-27
1
4
1
2
1
2