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December 2008

General Information

DDR3 SDRAM

1. DDR3 SDRAM Component Ordering Information

51  

:

  512Mb

1G 

:

      1Gb

2G

 :      

2Gb

4G

 :      

4Gb

04

 :

   x 4

08

 :

   x 8

16 

:

   x16    

3  

:

  4 Banks

4  

:

  8 Banks

5  

:

  16 Banks

3. DRAM Type

4. Density

5. Bit Organization 

6. # of Internal Banks


A
B
C
D
E
F
G
H

Z
H
J
M


L
Y

9. Package Type

8. Revision

10. Temp & Power 

1. SAMSUNG Memory : K

2. DRAM : 4

Revision

# of Internal Banks

Bit Organization

Density

DRAM Type

DRAM

SAMSUNG Memory

Interface (V

DD

, V

DDQ

)

Package Type

Temp & Power

1       2         3             4                5            6        7       8              9      10          11   

Speed

B  

:

 DDR3 SDRAM

:

 Commercial Temp.( 0

°

C ~ 85

°

C) & Normal Power

:

 Commercial Temp.( 0

°

C ~ 85

°

C) & Low Power

Commercial Temp.( 0

°

C ~ 85

°

C) & Low VDD(1.35V)

:

  FBGA (Lead-free)

:

  FBGA (Halogen-free & Lead-free)

:

  FBGA (Lead-free, DDP)

:

  FBGA (Halogen-free & Lead-free, DDP)

:

 1st Gen.

2nd Gen.

3rd Gen.

:

 4th Gen.

:

 5th Gen.

:

 6th Gen.

:

 7th Gen

:

 8th Gen

:

 9th Gen

11. Speed 

K  4   B  X  X  X  X  X  X  X  -  X  X  X  X

 :  

DDR3-800    (400MHz @ CL=6, tRCD=6, tRP=6)

 :  

DDR3-1066  (533MHz @ CL=7, tRCD=7, tRP=7)

 :  

DDR3-1333  (667MHz @ CL=9, tRCD=9, tRP=9)

 :  

DDR3-1600  (800MHz @ CL=11, tRCD=11, tRP=11)

F7
F8
H9
K0

6  

 SSTL (1.5V, 1.5V)

7. Interface ( V

DD

, V

DDQ

Summary of Contents for DDR3

Page 1: ...December 2008 General Information DDR3 SDRAM DDR3 SDRAM Product Guide December 2008 Memory Division...

Page 2: ...UNG Memory Interface VDD VDDQ Package Type Temp Power 1 2 3 4 5 6 7 8 9 10 11 Speed B DDR3 SDRAM Commercial Temp 0 C 85 C Normal Power Commercial Temp 0 C 85 C Low Power Commercial Temp 0 C 85 C Low V...

Page 3: ...ll FBGA Now K4B1G0846E HC L F7 F8 H9 K0 128M x 8 K4B1G1646E HC L F7 F8 H9 K0 64M x 16 96 ball FBGA 2Gb B die 8Banks K4B2G0446B HC L F7 F8 H9 512M x 4 78 ball FBGA Now K4B2G0846B HC L F7 F8 H9 256M x 8...

Page 4: ...nks in comp Interface 3 DDR3 SDRAM Module Ordering Information 1 1st Rev 3 3rd Rev C L Y Commercial Temp 0 C 85 C Normal Power Commercial Temp 0 C 85 C Low Power Commercial Temp 0 C 85 C Low VDD 1 35V...

Page 5: ...die 78 ball FBGA Now 256Mx 72 2GB M391B5673DZ1 F8 H9 128M x 8 18 pcs 1Gb D die 78 4 ball FBGA Now M391B5673EH1 F8 H9 K0 128M x 8 18 pcs 1Gb E die 78 ball FBGA Now 512Mx 64 4GB M378B5273BH1 F8 H9 256M...

Page 6: ...GA 1Q 09 M393B1K73BH1 CF7 F8 256M x 8 36 pcs 2Gb B die 4 78 ball FBGA Now M393B1K70BH1 CF7 F8 H9 512M x 4 36 pcs 2Gb B die 2 78 ball FBGA Now 2Gx 72 16GB M393B2K70BM1 CF7 F8 DDP 1G x 4 36 pcs 2Gb B di...

Page 7: ...1 CH9 0849 5 RDIMM RCD Information 1 RCD Identification in JEDEC Description in Module Label 2 Label Example 3 RCD Information Example Vendor Revision Module P N JEDEC Description On Label Inphi B2 M3...

Page 8: ...RK B A 11 00 0 10 J K L 0 80 0 80 Post Reflow 0 05 0 05 0 95 1 90 Bottom Top Bottom Top A1 9 00 0 10 11 00 0 10 0 10MAX 0 50 0 05 1 10 0 10 0 35 0 05 A B C D E F G H J L M N P R T 9 00 0 10 4 00 0 80...

Page 9: ...11 00 0 10 J K L 0 80 0 80 Post Reflow 0 05 0 05 0 95 1 90 Bottom Top Bottom Top A1 7 50 0 10 11 00 0 10 0 10MAX 0 50 0 05 1 10 0 10 0 35 0 05 A B C D E F G H J L M N P R T 7 50 0 10 6 00 Datum B Dat...

Page 10: ...BOTTOM VIEW 11 50 0 10 J K L 0 80 0 80 Post Reflow 0 50 0 05 0 95 1 90 0 10MAX 1 10 0 10 A1 9 00 0 10 11 50 0 10 0 35 0 05 TOP VIEW A B C D E F G H J L M N P R T 9 00 0 10 3 60 0 80 6 00 Datum B Datum...

Page 11: ...0 Detail B 5 00 Detail A 1 50 0 10 0 80 0 05 3 80 2x 2 10 0 15 x64 x72 240pin DDR3 SDRAM Unbuffered DIMM Units Millimeters 1 270 0 10 4 00 N A for x64 for x72 ECC A B 47 00 71 00 133 35 9 50 128 95 2...

Page 12: ...M x64 204pin DDR3 SDRAM Unbuffered SODIMM Units Millimeters 67 60 30 00 mm nom SPD Max 3 8 1 00 0 10 20 00 mm 0 10 A B M C 2X 4 00 0 10 0 10 A B M C 2X 1 80 OPTIONAL HOLES 0 25 MAX 2 55 Detail B Detai...

Page 13: ...30 17 80 Register 1 27 0 10 4 00 max 1 0 max D8 Register D3 D2 D1 D0 D7 D6 D5 D4 Address Command and Control lines D17 D12 D11 D10 D9 D16 D15 D14 D13 1 00 0 2 0 15 2 50 0 20 Detail B 5 00 Detail A 1...

Page 14: ...15 25 6 0 15 7 45 119 29 80 78 Green Line TIM Attatch Line 0 4 1 0 0 3 0 65 0 2 R0 2 R 0 1 1 25 6 0 15 0 15 1 3 1 3 2 2 0 1 2 6 0 2 1 FRONT PART Reg pedestal line Outside Inside Green Line TIM Attatch...

Page 15: ...n size 2 5 3 6 K text mark B or K punch press_stamp 6 8 0 1 43 9 39 3 0 2 29 77 R 1 5 0 1 0 3 Upper Bending Tilting Gap 0 5 3 CLIP PART 5 8 1 05 132 95 133 45 1 27 4 DDR3 RDIMM ASS Y View Reference th...

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