Samsung DCB-P850Z, Service Manual

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Circuit Operating Descriptions
13-12 Samsung Electronics
13-4 Memory Interface
13-4-1 FMI (Flash and peripheral memory interface)
1) Flash (U401) : 28F640J3D75, BGA Type,
This saves the Bootloader and the Main Software and provides an interface between
the CPU and the DDR SDRAM.
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Read Operation
The device supports four types of read modes: Read Array, Read Identifier,
Read Status, and CFI query. Upon power-up or return from reset, the device
defaults to read array mode. To change the device’s read mode, the appropriate read-mode
command must be written to the device for details regarding read status, read ID, and CFI query modes.
Upon initial device power-up or after exit from reset/power-down mode, the device automatically
resets to read array mode. Otherwise, write the appropriate read mode command
(Read Array, Read Query, Read Identifier Codes, or Read Status Register) to the CUI.
Six control signals dictate the data flow in and out of the component:
CE0, CE1, CE2, OE#, WE#, and RP#. The device must be enabled and OE# must be driven active
to obtain data at the outputs. CE0, CE1, and CE2 are the device selection controls and, when enabled ),
select the memory device. OE# is the data output (D[15:0]) control and, when active,
drives the selected memory data onto the I/O bus. WE# must be at VIH.
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Programming Operation
• Byte/Word Program
Byte/Word program is executed by a two-cycle command sequence.
Byte/Word program setup (standard 0x40 or alternate 0x10) is written followed by a second write
that specifies the address and data (latched on the rising edge of WE#).
The WSM then takes over, controlling the program and program verify algorithms internally.
After the program sequence is written, the device automatically outputs SRD when read.
The CPU can detect the completion of the program event by analyzing the STS signal or SR.7.
When program is complete, SR.4 should be checked. If a program error is detected,
the Status Register should be cleared. The internal WSM verify only detects errors for “1”s that do not
successfully program to “0”s.
The CUI remains in Read Status Register mode until it receives another command.
Reliable byte/word programming can only occur when VCC and VPEN are valid.
If a byte/word program is attempted while VPEN
≤
VPENLK, SR.4 and SR.3 will be set.
Successful byte/word programs require that the corresponding block lock-bit be cleared.
If a byte/word program is attempted when the corresponding block lock-bit is set, SR.1 and SR.4 will be set.