Circuit Operating Descriptions
Samsung Electronics
13-7
13-3-5 Graphics and display subsystem
The video decoder is based on the Omega2 cell and provides a memory-to-memory
decode into YC 4:2:0 macroblock format, it is able to provide simple resizing based on x2
and x0.5.
Composition is tile-based and requires multiple passes of the blitter engine, a tile RAM acts
as a cache for intermediate results and reduces the bandwidth overhead on the DDR
interface.
The blitter is able to combine two tiles on each pass whilst performing format conversion,
up/down sampling (for example resampling square pixel graphics), blending, arbitrary re-size,
antiflicker and so on.
Generally three passes are needed.
• The background color and still plane are combined.
• Video is added (YC 4:2:0 macroblock format).
• OSD is added.
The GDMA retrieves the final composition from main memory and delivers it to the digital
encoder which in turn drives the output video DAC.
1) Display
A tiled-based blitter display architecture is used, with the following display planes available:
• Background color,
• Still picture plane,
• Vdeo plane,
• On-screen display (OSD).
2) Picture plane
The picture plane can be used for still pictures and graphics display behind the video
plane. Images are stored using YCbCr 4:2:2 or 4:2:0 format. The picture plane can
perform zoom in (x2) and zoom out (x1/2), hardware unroll and wipes and fading-to-background
color.
3) OSD plane
The OSD plane is managed as a set of horizontal bands with a specification
comprising configuration, bitmap and, for CLUT formats, palette information for each
region. The OSD operates in one of two modes, palette mode or true color mode.
• Palette mode: Each region can be independently specified with a resolution of 2 bpp,
4 bpp or 8 bpp. Regions are frame based. Each region palette can support up to 256
colors with up to 24 bits resolution per color entry.
• True color mode: Each region can be independently specified with a 16 bpp
resolution in one of the following direct color formats: RGB565, ARGB1555, or ARGB444.
A vertical interfield, antiflicker filter is provided to reduce flicker on interlace displays. It
is available for both palette and true color modes.
4) Display mixing
Display planes are mixed by the blitter using alpha blending between planes. Mixing of
the OSD plane with the lower layers is achieved using one of the following on a per region basis.
• A 4-bit alpha blending component per region (true color mode and palette mode without antialiasing enabled).
• An individual 6-bit alpha component per color (palette mode with antialiasing enabled).
• Alpha with pixel (ARGB1555 or ARGB4444, true color mode only).
When mixing OSD regions the still picture layer and decoded video are output on the
composite outputs (YC and CVBS), component (RGB/YUV) and digital video outputs.
The capability for a separate VCR output is also supported.
Summary of Contents for DCB-P850Z
Page 13: ...3 2 Software Update Samsung Electronics MEMO ...
Page 19: ...4 6 Disassembly and Reassembly Samsung Electronics MEMO ...
Page 30: ...Samsung Electronics 6 1 6 Exploded View and Parts List 6 1 Ass y Chassis 6 2 ...
Page 33: ...Exploded View and Parts List 6 4 Samsung Electronics MEMO ...
Page 46: ...9 1 9 Wiring Diagram Samsung Electronics ...
Page 47: ...Wiring Diagram 9 2 MEMO Samsung Electronics ...
Page 51: ...PCB Diagrams 10 4 Samsung Electronics CONDUCTOR SIDE ...
Page 52: ...PCB Diagrams 10 5 Samsung Electronics 10 2 Front PCB COMPONENT SIDE CONDUCTOR SIDE ...
Page 53: ...PCB Diagrams 10 6 Samsung Electronics 10 3 S M P S PCB COMPONENT SIDE ...
Page 54: ...PCB Diagrams 10 7 Samsung Electronics CONDUCTOR SIDE ...
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Page 69: ...Schematic Diagrams 11 14 Samsung Electronics MEMO ...
Page 70: ...Samsung Electronics 12 1 12 Operating Instructions ...
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