Samsung 42LW5700, Service Manual

Page: 22 / 108

THERMAL THERMAL
THE SYMBOL MARK OF THIS SCHEMETIC DIAGRAM INCORPORATES
SPECIAL FEATURES IMPORTANT FOR PROTECTION FROM X-RADIATION.
FILRE AND ELECTRICAL SHOCK HAZARDS, WHEN SERVICING IF IS
ESSENTIAL THAT ONLY MANUFATURES SPECFIED PARTS BE USED FOR
THE CRITICAL COMPONENTS IN THE SYMBOL MARK OF THE SCHEMETIC.
DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]
DDR1_DATA[0]
DDR1_DATA[1]
DDR1_DATA[2]
DDR1_DATA[3]
DDR1_DATA[4]
DDR1_DATA[5]
DDR1_DATA[6]
DDR1_DATA[7]
DDR1_DATA[8]
DDR1_DATA[9]
DDR1_DATA[10]
DDR1_DATA[11]
DDR1_DATA[12]
DDR1_DATA[13]
DDR1_DATA[14]
DDR1_DATA[15]
DDR1_A[0]
DDR1_A[1]
DDR1_A[2]
DDR1_A[3]
DDR1_A[4]
DDR1_A[5]
DDR1_A[6]
DDR1_A[7]
DDR1_A[8]
DDR1_A[9]
DDR1_A[10]
DDR1_A[11]
DDR1_A[12]
DDR0_A[0]
DDR0_A[1]
DDR0_A[2]
DDR0_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR0_A[7]
DDR0_A[8]
DDR0_A[9]
DDR0_A[10]
DDR0_A[11]
DDR0_A[12]
DDR0_DATA[0]
DDR0_DATA[1]
DDR0_DATA[2]
DDR0_DATA[3]
DDR0_DATA[4]
DDR0_DATA[5]
DDR0_DATA[6]
DDR0_DATA[7]
DDR0_DATA[8]
DDR0_DATA[9]
DDR0_DATA[10]
DDR0_DATA[11]
DDR0_DATA[12]
DDR0_DATA[13]
DDR0_DATA[14]
DDR0_DATA[15]
DDR0_A[0]
DDR0_A[1]
DDR0_A[2]
DDR0_A[3]
DDR0_A[4]
DDR0_A[5]
DDR0_A[6]
DDR0_A[7]
DDR0_A[8]
DDR0_A[9]
DDR0_A[10]
DDR0_A[11]
DDR0_A[12]
DDR0_DATA[0]
DDR0_DATA[1]
DDR0_DATA[2]
DDR0_DATA[3]
DDR0_DATA[4]
DDR0_DATA[5]
DDR0_DATA[6]
DDR0_DATA[7]
DDR1_DATA[0]
DDR1_DATA[1]
DDR1_DATA[2]
DDR1_DATA[3]
DDR1_DATA[4]
DDR1_DATA[5]
DDR1_DATA[6]
DDR1_DATA[7]
DDR1_DATA[9]
DDR1_DATA[10]
DDR1_DATA[14]
DDR1_DATA[8]
DDR1_DATA[12]
DDR1_DATA[15]
DDR1_DATA[11]
DDR1_DATA[13] DDR0_DATA[13]
DDR0_DATA[11]
DDR0_DATA[14]
DDR0_DATA[9]
DDR0_DATA[8]
DDR0_DATA[12]
DDR0_DATA[10]
DDR0_DATA[15]
DDR0_A[2]
DDR0_A[3]
DDR0_A[7]
DDR0_A[10]
DDR0_A[12]
DDR0_A[13]
DDR0_A[9]
DDR0_A[1]
DDR0_A[0]
DDR0_A[6]
DDR0_A[8]
DDR0_A[4]
DDR0_A[11]
DDR0_A[5] DDR1_A[5]
DDR1_A[4]
DDR1_A[9]
DDR1_A[3]
DDR1_A[1]
DDR1_A[6]
DDR1_A[8]
DDR1_A[13]
DDR1_A[0]
DDR1_A[10]
DDR1_A[7]
DDR1_A[11]
DDR1_A[2]
DDR1_A[12]
C224
0.1uF
DDR1_BA[0]
DDR1_BA[1]
DDR0_DQS[1]
DDR0_DQS_N[0]
C205
0.1uF
DDR0_CLKN
DDR1_DQS[0]
C235
0.1uF
DDR1_DM[1]
DDR1_BA[0]
DDR1_CASN
C208
0.1uF
C222
0.1uF
R219 240
1%
DDR0_DQS[0]
DDR1_ODT
DDR0_DM[1]
C226
0.1uF
C231
0.1uF
DDR1_WEN
C214
0.1uF
DDR0_CKE
DDR1_RASN
DDR0_CLK
DDR1_CASN
DDR1_ODT
DDR0_CLK
DDR0_DM[0]
DDR0_CASN
DDR1_DQS_N[0]
DDR1_CLKN
DDR0_BA[2]
DDR0_ODT
C200
10uF
10V
DDR1_CKE
DDR1_CLKN
DDR0_BA[2]
DDR1_DQS[1]
DDR1_DM[0]
DDR1_RASN
DDR1_WEN
C227
0.1uF
C211
0.1uF
DDR0_BA[1]
C284
0.1uF
C216
0.1uF
DDR1_DM[0]
DDR0_WEN
DDR1_CKE
C213
0.1uF
DDR0_RESET_N
C225
0.1uF
C230
0.1uF
C219
0.1uF
DDR1_DM[1]
DDR1_BA[1]
DDR1_CLK
DDR0_DQS_N[1]
DDR0_WEN
R228
240 1%
DDR0_RASN
DDR0_DQS_N[1]
DDR0_BA[0]
DDR0_CLKN
DDR1_RESET_N
R204
240 1%
DDR0_ODT
DDR1_DQS_N[1]
DDR0_DQS_N[0]
DDR0_RASN
DDR0_CASN
DDR0_CKE
DDR0_RESET_N
C228
0.1uF
DDR0_DM[0]
DDR0_BA[1]
DDR1_CLK
DDR1_DQS[1]
DDR1_BA[2]
DDR1_DQS_N[0]
C204
0.1uF
DDR1_BA[2]
C221
0.1uF
R214 240
1%
C229
0.1uF
DDR1_DQS[0] DDR0_DQS[0]
DDR1_DQS_N[1]
DDR0_DQS[1]
DDR0_BA[0]
C279
0.1uF
DDR0_DM[1]
C218
0.1uF
DDR1_RESET_N
DDR0_A[0-13]
DDR0_DATA[0-15]
DDR1_A[0-13]
DDR1_DATA[0-15]
DDR0_A[0-13]
DDR0_DATA[0-15]
DDR1_A[0-13]
DDR1_DATA[0-15]
AR204
68
DDR0_CASN
C207
0.1uF
16V
AR202
68
DDR0_WEN
C215
0.1uF
16V C217
0.1uF
16V
AR200
68
C220
0.1uF
16V C209
0.1uF
16V
DDR0_ODT
AR203
68
DDR0_BA[1]
DDR0_BA[0]
C203
0.1uF
16V
AR201
68
R205
68
DDR0_RASN
C212
0.1uF
16V
DDR0_BA[2]
AR207
68
C296
0.1uF
16V C289
0.1uF
16V
DDR1_BA[1]
DDR1_BA[2]
DDR1_BA[0]
DDR1_ODT
AR205
68
C1203
0.1uF
16V
R229
68
DDR1_WEN
AR206
68
C293
0.1uF
16V
DDR1_CASN
DDR1_RASN
C298
0.1uF
16V C1201
0.1uF
16V C291
0.1uF
16V
AR209
68
AR208
68
C250
1000pF
R213
1K
1%
R211
1K
1%
C237
0.1uF
C245
0.1uF
R209
1K
1%
C246
0.1uF
R206
1K
1%
R208
1K
1%
C249
1000pF
R207
1K
1%
R212
1K
1%
C242
1000pF
C241
1000pF
C238
0.1uF
R210
1K
1%
R217
1K
1%
R215
1K
1%
C264
1000pF
R220
1K
1%
C260
0.1uF
C269
0.1uF
C273
1000pF
R221
1K
1%
R216
1K
1%
R218
1K
1%
C261
0.1uF
R222
1K
1%
C270
0.1uF
C265
1000pF
R223
1K
1%
C274
1000pF
+0.75V_VREF0_D0 +0.75V_VREF0_D1 +0.75V_VREF1_D1 +0.75V_VREF1_D0
+1.5VQ0
+0.75V_VTT1
+0.75V_VREF1_D0
+1.5VQ1 +1.5VQ1
+1.5VQ1
+0.75V_VTT1
+1.5V1 +1.5VQ1
+1.5VQ1 +0.75V_VREF1_D1
+1.5VQ0 +1.5VQ0 +1.5V0
+1.5VQ0
+0.75V_VREF0_M1
+1.5VQ0
+0.75V_VREF0_D1 +0.75V_VREF0_D0
+1.5VQ0 +0.75V_VREF0_M0
+0.75V_VTT0
+1.5VQ1
+0.75V_VREF1_M1
+0.75V_VREF1_M0
+0.75V_VREF1_D0
+1.5VQ1
+0.75V_VREF1_D1
+0.75V_VREF0_D0
+0.75V_VREF0_D1
+1.5VQ0
+0.75V_VREF0_M0
+0.75V_VREF0_M1
L202
CIC21J501NE
L203
CIC21J501NE
+1.5VQ0
+1.5VQ0
R200
10K
R226
10K
+1.5VQ1
+0.75V_VREF1_M1
DDR0_A[0-13]
DDR1_A[0-13]
C253
0.1uF
16V C257
0.1uF
16V C276
0.1uF
16V C281
0.1uF
16V
+0.75V_VTT0
R203
100 1%
R227
100 1%
+0.75V_VREF1_M0
C287
10uF
R201
10K
C288
0.1uF
C201
10uF
+3.3VD
+0.75V_VTT0
C202
10uF
C290
4700pF
R202
10K
C206
10uF
C223
1000pF
+1.5VQ0
C210
10uF
+0.75V_VTT1
R224
10K
+3.3VD
C1224
4700pF
+1.5VQ1
C1219
10uF
C294
10uF
C1222
10uF
C1221
1000pF
C1218
10uF C1220
10uF C1223
0.1uF
R225
10K
L204
CIS21J121
L205
CIS21J121
L206
CIS21J121
L207
CIS21J121
C1227
0.1uF
C1207
0.1uF
C1225
0.1uF
C1226
0.1uF
C1233
0.22uF
6.3V
C1229
0.22uF
6.3V
C244
0.1uF
C1231
0.22uF
6.3V
C1234
0.22uF
6.3V C1235
0.22uF
6.3V
C1228
0.22uF
6.3V C1230
0.22uF
6.3V
C1232
0.22uF
6.3V
+1.5VQ1
+1.5VQ0
C247
0.1uF
C1236
0.22uF
6.3V C259
0.1uF
C292
10uF
10V
C1206
0.1uF
C1205
0.1uF
C1202
0.1uF
C1215
0.1uF
C297
0.1uF
C1200
0.1uF
C1212
0.1uF
+1.5VQ1
C1210
0.1uF
H5TQ1G63DFR-PBC
IC201
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
H5TQ1G63DFR-PBC
IC202
A0
N3
A1
P7
A2
P3
A3
N2
A4
P8
A5
P2
A6
R8
A7
R2
A8
T8
A9
R3
A10/AP
L7
A11
R7
A12/BC
N7
A13
T3
A15
M7
BA0
M2
BA1
N8
BA2
M3
CK
J7
CK
K7
CKE
K9
CS
L2
ODT
K1
RAS
J3
CAS
K3
WE
L3
RESET
T2
DQSL
F3
DQSL
G3
DQSU
C7
DQSU
B7
DML
E7
DMU
D3
DQL0
E3
DQL1
F7
DQL2
F2
DQL3
F8
DQL4
H3
DQL5
H8
DQL6
G2
DQL7
H7
DQU0
D7
DQU1
C3
DQU2
C8
DQU3
C2
DQU4
A7
DQU5
A2
DQU6
B8
DQU7
A3
VREFCA
M8
VREFDQ
H1
ZQ
L8
VDD_1
B2
VDD_2
D9
VDD_3
G7
VDD_4
K2
VDD_5
K8
VDD_6
N1
VDD_7
N9
VDD_8
R1
VDD_9
R9
VDDQ_1
A1
VDDQ_2
A8
VDDQ_3
C1
VDDQ_4
C9
VDDQ_5
D2
VDDQ_6
E9
VDDQ_7
F1
VDDQ_8
H2
VDDQ_9
H9
NC_1
J1
NC_2
J9
NC_3
L1
NC_4
L9
NC_6
T7
VSS_1
A9
VSS_2
B3
VSS_3
E1
VSS_4
G8
VSS_5
J2
VSS_6
J8
VSS_7
M1
VSS_8
M9
VSS_9
P1
VSS_10
P9
VSS_11
T1
VSS_12
T9
VSSQ_1
B1
VSSQ_2
B9
VSSQ_3
D1
VSSQ_4
D8
VSSQ_5
E2
VSSQ_6
E8
VSSQ_7
F9
VSSQ_8
G1
VSSQ_9
G9
C1237
1uF
6.3V
C1238
1uF
6.3V
IC200
TPS51200DRCR
3
VO
2
VLDOIN
4
PGND
1
REFIN
5
VOSNS
6
REFOUT
7
EN
8
GND
9
PGOOD
10
VIN
11
[EP]
IC203
TPS51200DRCR
3
VO
2
VLDOIN
4
PGND
1
REFIN
5
VOSNS
6
REFOUT
7
EN
8
GND
9
PGOOD
10
VIN
11
[EP]
IC101
LG1121A
DDR0_A[0]
AJ33
DDR0_A[1]
J34
DDR0_A[2]
AK34
DDR0_A[3]
AG33
DDR0_A[4]
K34
DDR0_A[5]
AG34
DDR0_A[6]
K33
DDR0_A[7]
AH33
DDR0_A[8]
K32
DDR0_A[9]
AK33
DDR0_A[10]
L34
DDR0_A[11]
J33
DDR0_A[12]
L32
DDR0_A[13]
AJ34
DDR0_A[14]
J32
DDR0_DQ[0]
AB33
DDR0_DQ[1]
P34
DDR0_DQ[2]
AB34
DDR0_DQ[3]
P33
DDR0_DQ[4]
AC34
DDR0_DQ[5]
N33
DDR0_DQ[6]
AC33
DDR0_DQ[7]
N34
DDR0_DQ[8]
T34
DDR0_DQ[9]
Y33
DDR0_DQ[10]
R34
DDR0_DQ[11]
AA33
DDR0_DQ[12]
U33
DDR0_DQ[13]
Y34
DDR0_DQ[14]
T33
DDR0_DQ[15]
W34
DDR0_CK
M34
DDR0_CK_N
M33
DDR0_DQS[0]
W33
DDR0_DQS_N[0]
V34
DDR0_DQS[1]
V33
DDR0_DQS_N[1]
U34
DDR0_CKE
M32
DDR0_WE_N
AE34
DDR0_RAS_N
AD33
DDR0_CAS_N
AD34
DDR0_ODT
AE33
DDR0_DM[0]
R33
DDR0_DM[1]
AA34
DDR0_BA[0]
AF33
DDR0_BA[1]
L33
DDR0_BA[2]
AF34
DDR0_RST_N
AH34
DDR0_ZQ_CAL
AE32
DDR0_VREF0
W31
DDR0_VREF1
N31
DDR0_VDDQ_1
J31
DDR0_VDDQ_2
K31
DDR0_VDDQ_3
L31
DDR0_VDDQ_4
P31
DDR0_VDDQ_5
R31
DDR0_VDDQ_6
T31
DDR0_VDDQ_7
U31
DDR0_VDDQ_8
Y31
DDR0_VDDQ_9
AA31
DDR0_VDDQ_10
AB31
DDR0_VDDQ_11
AC31
DDR0_VDDQ_12
AD31
DDR0_VDDQ_13
AE31
DDR0_VDDQ_14
AF31
DDR0_VDDQ_15
AG31
DDR0_VDDQ_16
AH31
DDR1_A[0]
AM17
DDR1_A[1]
AN33
DDR1_A[2]
AP16
DDR1_A[3]
AP19
DDR1_A[4]
AN32
DDR1_A[5]
AM18
DDR1_A[6]
AM32
DDR1_A[7]
AN18
DDR1_A[8]
AP33
DDR1_A[9]
AP17
DDR1_A[10]
AN31
DDR1_A[11]
AM33
DDR1_A[12]
AP32
DDR1_A[13]
AN17
DDR1_A[14]
AN34
DDR1_DQ[0]
AM22
DDR1_DQ[1]
AM28
DDR1_DQ[2]
AN22
DDR1_DQ[3]
AP29
DDR1_DQ[4]
AN21
DDR1_DQ[5]
AM29
DDR1_DQ[6]
AP22
DDR1_DQ[7]
AN29
DDR1_DQ[8]
AN27
DDR1_DQ[9]
AN24
DDR1_DQ[10]
AP28
DDR1_DQ[11]
AN23
DDR1_DQ[12]
AP27
DDR1_DQ[13]
AP24
DDR1_DQ[14]
AM27
DDR1_DQ[15]
AM24
DDR1_CK
AP30
DDR1_CK_N
AN30
DDR1_DQS[0]
AP25
DDR1_DQS_N[0]
AN25
DDR1_DQS[1]
AP26
DDR1_DQS_N[1]
AN26
DDR1_CKE
AP31
DDR1_WE_N
AP20
DDR1_RAS_N
AP21
DDR1_CAS_N
AM20
DDR1_ODT
AN20
DDR1_DM[0]
AN28
DDR1_DM[1]
AP23
DDR1_BA[0]
AM19
DDR1_BA[1]
AM31
DDR1_BA[2]
AN19
DDR1_RST_N
AP18
DDR1_ZQ_CAL
AM21
DDR1_VREF0
AJ22
DDR1_VREF1
AJ26
DDR1_VDDQ_1
AK17
DDR1_VDDQ_2
AK18
DDR1_VDDQ_3
AK19
DDR1_VDDQ_4
AK20
DDR1_VDDQ_5
AK21
DDR1_VDDQ_6
AK22
DDR1_VDDQ_7
AK23
DDR1_VDDQ_8
AK24
DDR1_VDDQ_9
AK25
DDR1_VDDQ_10
AK26
DDR1_VDDQ_11
AK27
DDR1_VDDQ_12
AK28
DDR1_VDDQ_13
AK29
DDR1_VDDQ_14
AK30
DDR1_VDDQ_15
AK31
DDR1_VDDQ_16
AK32
LG1121_DDR
2010. 10. 20
2
LG1121 GP3
7
DDR3 1.5V/0.75V Decap
- Place these caps near IC101
DDR3 1.5V/0.75V Decap
- Place these caps near IC101
DDR3 1.5V Decaps - Place these caps near Memory
DDR0 PHY VTT DDR1 PHY VTT DDR0 PHY VREF DDR1 PHY VREF
Close to REFOUT pin Close to REFOUT pin
DDR3 1.5V beCaps - Place these caps near Memory