User Manual
RTX Nexus ICE-III
Date:
2017-07-11
File
: Nice_user_manual.docx
Ref.:
LEH
Rev.
: 3.0
Page:
6
of
8
pages
This document and the information contained is property of RTX A/S, Denmark. Unauthorized copying is not allowed. The in-
formation in this document is believed to be correct at the time of writing. RTX A/S reserves the right at any time to change said
content, circuitry and specifications.
4 Reference
4.1 20-pins header
1
IO
V
C
C
2
G
N
D
3
5
7
9
1
1
1
3
1
5
1
7
1
9
4
6
8
1
0
1
2
1
4
1
6
1
8
2
0
T
R
S
T
T
D
I
T
M
S
T
C
K
R
T
C
K
T
D
O
R
E
S
E
T
R
D
Y
N
C
G
N
D
G
N
D
G
N
D
G
N
D
J
T
IO
/S
W
D
IO
U
T
X
U
R
X
S
W
C
L
K
N
C
L
E
D
B
u
tt
o
n
#
Pin
Description
1
IOVCC
Target I/O voltage input. RTX Nexus ICE-III adapts the voltage for
the other I/O ports to the voltage detected on this pin.
The supported range is 1V8-3V3.
3
TRST
5-wire JTAG: Test logic reset.
5
TDI
5-wire JTAG: Test data input.
7
TMS
5-wire JTAG: Test mode select.
9
TCK
5-wire JTAG: Test clock.
11
RTCK
5-wire JTAG: Return clock.
13
TDO
5-wire JTAG: Test data output.
15
RESET
5-wire JTAG: Processor reset.
17
RDY
5-wire JTAG: Ready (SDI+).
2-8, 20
GND
Ground.
10
JTIO
1-wire JTAG: I/O pin.
10
SWDIO
2-wire SWD: I/O pin.
12
UTX
UART transmit.
14
URX
UART receive.
16
SDWCLK
2-wire SWD: Clock pin.
