RTS DV 2400 Series, Service Manual

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DV-2400
3
CIRCUIT DESCRIPTION
„
Squelch Circuit
The detection output from the FM IF IC (U200) passes through a noise amplifier (U201 2/2) to detect
noise. A voltage is applied to the CPU (U2). The CPU controls squelch according to the voltage (SQIN)
level. The signal from the RSSI pin of U200 is used for S-meter. The electric field strength of the receive
signal can be known before the SQIN voltage is input to the CPU, and the scan stop speed is improved.
U200
SYSTEM
CPU
U2 NOISE AMP
U201
IF
SQ
RSSI
SQIN
RSSI
P0 0
P0 4
Fig. 5 Squelch Circuit
PLL frequency synthesizer
The PLL circuit generates the first local oscillator signal for reception and the RF signal for transmission.
„
PLL
The frequency step of the PLL circuit is 5 or 6.25kHz. A 19.200MHz reference oscillator signal is divided
at U205 by a fixed counter to produce the 5 or 6.25kHz reference frequency. The voltage controlled
oscillator (VCO) output signal is buffer amplified by Q211, then divided in U205 by a dualmodule
programmable counter. The divided signal is compared in phase with the 5 or 6.25kHz reference signal in
the phase comparator in U205. The output signal from the phase comparator is filtered through a low-pass
filter and passed to the VCO to control the oscillator frequency. (See Fig. 6.)
„
VCO
The operating frequency is generated by Q217 in transmit mode and Q216 in receive mode. The
oscillator frequency is controlled by applying the VCO control voltage, obtained from the phase
comparator, to the varactor diodes (D219 and D221 in transmit mode and D218 and D220 in receive
mode). The TX/RX pin is set high in receive mode causing Q201 and Q218 to turn Q217 off, and turn
Q216 on. The TX/RX pin is set low in transmit mode. The outputs from Q216 and Q217 are amplified by
Q210 and sent to the RF amplifiers. (See Fig. 6.)
.
COMPARATOR
PHASE
CHARGE
PUMP
U2 05 :PL L IC
REF OSC
I/N
I/M
PLL DATA
LPF
Q2 11
TX VCO
Q2 17
BUFF AMP
Q2 10
AMP
1 9.2 00 M Hz
Q2 01 ,Q21 8
T/R SW
RX VCO
Q2 16
RF amplifiers
P45 (CPU)
D2 19 ,D22 1
D2 18 ,D22 0
5 KHz /6.2 5KHz
5 KHz /6.2 5KHz
Fig. 6 PLL circuit
„
UNLOCK Circuit
During reception, the RXC signal goes high, the TXC signal goes low, and Q108 turns on. Q101 turns
on and a voltage is applied to (8R). During transmission, the RXC signal goes low, the TXC signal goes