DM5210 analog input module 4-13 RTD Embedded Technologies, Inc.
if the second request has a higher priority. The priority level is based on the number of the IRQ; IRQ0 has the highest
priority, IRQ1 is second-highest, and so on through IRQ7, which has the lowest. Many of the IRQs are used by the
standard system resources. IRQ0 is used by the system timer, IRQ1 is used by the keyboard, IRQ3 by COM2, IRQ4
by COM1, and IRQ6 by the disk drives. Therefore, it is important for you to know which IRQ lines are available in
your system for use by the 210/5210.
• 8259 Programmable Interrupt Controller
The chip responsible for handling interrupt requests in the PC is the 8259 Programmable Interrupt Controller.
To use interrupts, you need to know how to read and set the 8259’s interrupt mask register (IMR) and how to send
the end-of-interrupt (EOI) command to the 8259.
• Interrupt Mask Register (IMR)
Each bit in the interrupt mask register (IMR) contains the mask status of an IRQ line; bit 0 is for IRQ0, bit 1 is
for IRQ1, and so on. If a bit is set (equal to 1), then the corresponding IRQ is masked and it will not generate an
interrupt. If a bit is clear (equal to 0), then the corresponding IRQ is unmasked and can generate interrupts. The IMR
is programmed through port 21H.
For all bits:
0 = IRQ unmasked (enabled)
1 = IRQ masked (disabled)
I/O Port 21H
• End-of-Interrupt (EOI) Command
After an interrupt service routine is complete, the 8259 interrupt controller must be notified. This is done by
writing the value 20H to I/O port 20H.
• What Exactly Happens When an Interrupt Occurs?
Understanding the sequence of events when an interrupt is triggered is necessary to properly write software
interrupt handlers. When an interrupt request line is driven high by a peripheral device (such as the 210/5210), the
interrupt controller checks to see if interrupts are enabled for that IRQ, and then checks to see if other interrupts are
active or requested and determines which interrupt has priority. The interrupt controller then interrupts the processor.
The current code segment (CS), instruction pointer (IP), and flags are pushed on the stack for storage, and a new CS
and IP are loaded from a table that exists in the lowest 1024 bytes of memory. This table is referred to as the inter-
rupt vector table and each entry is called an interrupt vector. Once the new CS and IP are loaded from the interrupt
vector table, the processor begins executing the code located at CS:IP. When the interrupt routine is completed, the
CS, IP, and flags that were pushed on the stack when the interrupt occurred are now popped from the stack and
execution resumes from the point where it was interrupted.
• Using Interrupts in Your Programs
Adding interrupts to your software is not as difficult as it may seem, and what they add in terms of performance
is often worth the effort. Note, however, that although it is not that hard to use interrupts, the smallest mistake will
often lead to a system hang that requires a reboot. This can be both frustrating and time-consuming. But, after a few
tries, you’ll get the bugs worked out and enjoy the benefits of properly executed interrupts. In addition to reading the
following paragraphs, study the INTRPTS source code included on your 210/5210 program disk for a better under-
standing of interrupt program development.
• Writing an Interrupt Service Routine (ISR)
The first step in adding interrupts to your software is to write the interrupt service routine (ISR). This is the
routine that will automatically be executed each time an interrupt request occurs on the specified IRQ. An ISR is
different than standard routines that you write. First, on entrance, the processor registers should be pushed onto the
7
Q
R
I
6
Q
R
I
5
Q
R
I
4
Q
R
I
3
Q
R
I
2
Q
R
I
1
Q
R
I
0
Q
R
I
Artisan Technology Group - Quality Instrumentation ... Guaranteed | (888) 88-SOURCE | www.artisantg.com
