18/27
TO-247N(-4L) Half-Bridge Evaluation Board
User’s Guide
© 2022 ROHM Co., Ltd.
No. 63UG0
60E
Rev.001
2022.2
9.4 Two-level inverter circuit
Figure 19 shows the operation test circuit for a 2-level inverter with a half-bridge configuration.
Figure 19 Operation test circuit for a 2-level inverter circuit
First, prepare a pulse generator and connect CLK signals to the IN_H_CLK and IN_L_CLK pins (CN1, CN101 pin 1).
Connect the 12 V power supply for control to the Vcc pin (CN201) and the load inductance to the Vsw pin (T2).
Prepare two
high-voltage HVdc power supplies with the same voltage, connect them in series, and connect the upper one to the HVdc pin
(T1) and the lower one to the PGND pin (T3). Connect a smoothing capacitor and an AC load to one side of the load inductance
and connect its return line to the middle point of the series-connected high-voltage HVdc power supply.
When the AC output is on the + side, the H-side switches, and when it is on the - side, the L-side switches, and by controlling
the duty cycle of the CLK signal, a sinusoidal voltage is output.
The operating procedure is as follows.
①
Turn on the +12 V power supply.
②
Set the switching frequency and duty ratio using the pulse generator and input the CLK signal.
③
Turn on the HVdc power supply.
④
Adjust the output current with an AC load device.
When increasing the load current, pay attention to the heat generation of the evaluation device, and if necessary, install a heat
sink capable of sufficient cooling or consider the ambient temperature.
Pulse
Generator
(+5V output)
AC
Load
PGND
HVdc
DUT_HS
DUT_LS
HS-GADJ
LS-GADJ
IN_H_CLK
IN_L_CLK
LDO
Vcc1
DCR
Vsw
Vcc
ICAP
SNB
SGND
PGND
PGND
PGND
PGND
SGND
HS_GD
PRIMERY
SECONDERY
BD7F200
HS
Gate Power
LS_GD
LS
Gate Power
BM61M41
BD7F200
BM61M41
VEE2
VCC2
VEE2
VCC2
Vcc1
HS_GSC
LS_GSC
UVLO2
UVLO2
RCD-SNB
RCD-SNB
HS-
VEESEL
LS-
VEESEL
SGND
VEE2
GND2
GND2
UVLO
UVLO1
UVLO
UVLO1
LS_CS
