Rohm LAPIS ML22594 MB Series, Manual

Page: 13 / 73

FEDL22594-06
ML22594-XXX
13/73
AC Characteristics (2) CPU serial interface
DV
DD
= SPV
DD
= 4.5 to 5.5 V, IOV
DD
= 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta =
−
40 to +105°C
Parameter Symbol Condition Min. Typ. Max. Unit
SCK input enable time from CSB fall t
ESCK
— 100 — — ns
SCK hold time from CSB rise t
CSH
— 100 — — ns
Data floating time from CSB rise t
DOZ
R
L
= 3 k
Ω
— — 100 ns
Data setup time from SCK rise t
DIS1
DIPH = “L” 50 — — ns
Data hold time from SCK rise t
DIH1
DIPH = “L” 50 — — ns
Data output delay time from SCK fall t
DOD1
DIPH = “L” — — 90 ns
Data setup time from SCK fall t
DIS2
DIPH = “H” 50 — — ns
Data hold time from SCK fall t
DIH2
DIPH = “H” 50 — — ns
Data output delay time from SCK rise t
DOD2
DIPH = “H” — — 90 ns
SCK “H” level pulse width t
SCKH
— 100 — — ns
SCK “L” level pulse width t
SCKL
— 100 — — ns
CBUSYB output delay time from SCK rise t
DBSY1
DIPH = “L” — — 90 ns
CBUSYB output delay time from SCK fall t
DBSY2
DIPH = “H” — — 90 ns
Note: Output pin load capacitance = 45 pF (Max.)
AC Characteristics (3) External ROM serial interface
DV
DD
= SPV
DD
= 4.5 to 5.5 V, IOV
DD
= 2.7 to 5.5 V, DGND = SPGND = 0 V, Ta =
−
40 to +105°C
Parameter Symbol Condition Min. Typ. Max. Unit
ESCK input enable time from ECSB fall edge t
ECSS
f
OSC
= 4.096 MHz 50 — — ns
ESCK input hold time from ECSB rise edge t
ECSH
f
OSC
= 4.096 MHz 50 — — ns
Data setup time from ESCK rise edge t
EDIS
f
OSC
= 4.096 MHz 10 — — ns
Data hold time from ESCK rise edge t
EDIH
f
OSC
= 4.096 MHz 10 — — ns
Data output delay time from ESCK rise edge t
EDOD
f
OSC
= 4.096 MHz — — 5 ns
ESCK clock frequency t
ESCKF
f
OSC
= 4.096 MHz 16.0 16.384 16.5 MHz
ESCK “H” level pulse width t
ESCKH
f
OSC
= 4.096 MHz 26 — — ns
ESCK “L” level pulse width t
ESCKL
f
OSC
= 4.096 MHz 26 — — ns
Data output delay time from FLW rise edge. t
EFLH
— — — 1 ms
Data output delay time from FLW fall edge. t
EFHL
— — — 1 ms
Note: Output pin load capacitance = 45 pF (Max.)