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TECHNICAL NOTE

HDMI Switch ICs 

3 for input 1 output switch with 
Termination sense 
correspondence 
(Sync with HPD_SINK) 

BU16028KV 

 

 
 

Description 

BU16028KV is 3 for input 1 output HDMI/DVI switch LSI. Each port supports 2.25Gbps. (HDMI 1.3a) 
This device control is simple. It requires only 3.3V source and a few GPIO controls.   
Terminated resistors(50

Ω

) are integrated at input port. When channel is not selected, termination resistors are turned off. 

TMDS inputs are high impedance.   
This device is integrated equalization function and DDC buffer function, so it can adapt long cable. 

         
 

Features 

 

Supports 2.25 Gbps signaling rate for 480i/p, 720i/p, and 1080i/p resolution to 12-bit color depth 

 

Compatible with HDMI 1.3a 

 

5V tolerance to all DDC and HPD_SINK inputs 

 

Integrated DDC buffer 

 

Integrated switchable 50

Ω

receiver termination 

 

Integrated equalizer circuit to adapt long cable 

 

HBM ESD protection exceeds 10kV 

 

3.3V fixed supply to TMDS I/Os 

 

64Pin VQFP package 

 

ROHS compatible 

 

Applications 

 

Digital TV 

 

DVD Player 

 

Set-Top-Box 

 

Audio Video Receiver 

 

Digital Projector 

 

DVI or HDMI Switch Box 

 
 
 
 
 
 
 
 
 
 
 

Sep. 2008 

Summary of Contents for BU16028KV

Page 1: ...S inputs are high impedance This device is integrated equalization function and DDC buffer function so it can adapt long cable Features Supports 2 25 Gbps signaling rate for 480i p 720i p and 1080i p...

Page 2: ...2 17 OUTSIDE DIMENSION CHART Fig 1 1 Outside dimension chart Lot No BU16028KV 1PIN MARK...

Page 3: ...S1 S2 HPD_SINK SCL_SINK SDA_SINK HPD1 HPD2 HPD3 SCL1 SDA1 SCL2 SDA2 SCL3 SDA3 TMDS R X TMDS R X TMDS R X TMDS R X R INT R INT V CC R INT R INT V CC R INT R INT V CC R INT R INT V CC VSADJ HPD_SINK TM...

Page 4: ...SDA3 SCL3 46 37 38 39 40 41 42 43 44 45 48 47 34 33 36 35 28 27 26 25 24 32 31 30 29 3 12 11 10 9 8 7 6 5 4 1 2 14 13 16 15 A31 GND B34 A34 VSADJ SCL_SINK GND SDA_SINK HPD_SINK S1 Vcc Vcc A11 B11 SCL1...

Page 5: ...urce port 3 hot plug detector output status pin HPD_SINK 31 I Sink port hot plug detector input status pin Reserve1 34 I O Set to HIGH LOW OPEN Reserve2 49 I O Non Connect Pin SCL1 37 I O Source port...

Page 6: ...Anm Bnm 50 VDD TMDS Input Stage Ym Zm 10mA TMDS Output Stage R Side I2C Input Output Stage SCL SDA VDD VDD VDD VDD VDD SCL_SINK SDA_SINK HPD_SINK HPDn VDD HPD Output Stage T Side I2C Input Output Sta...

Page 7: ...SCL3 SDA3 L L H H H L None Z All terminations are disconnected None Z Are pulled HIGH by external pull up termination H H H L H H Disallowed indeterminate State All terminations are disconnected SCL1...

Page 8: ...68 k AVCC TMDS Output termination voltage see Figure 5 1 3 3 3 3 6 V RT Termination resistance see Figure 5 1 45 50 55 Signaling rate 0 2 25 Gbps CONTROL PINS S1 S2 VIH LVTTL High level input voltage...

Page 9: ...W TMDS DIFFERENTIAL PINS A B Y Z VOH Single ended high level output voltage See Figure 5 2 AVcc 3 3V RT 50 AVcc 200 Avcc 50 mV VOL Single ended low level output voltage AVcc 600 Avcc 400 mV VSWING Sin...

Page 10: ...2 4 5 5 V VIL Low level input voltage 0 3 0 8 V IlKR Input leak current VI 5 5V 10 10 uA IlKR Input leak current VI Vcc 10 10 uA IOHR High level output current VO 3 6V 10 10 uA IILR Low level input cu...

Page 11: ...low level output Tx to Rx 200 ns tpdLHRT DDC Propagation delay time low to high level output Rx to Tx RL 1 67k CL 400pF 500 ns tpdHLRT DDC Propagation delay time high to low level output Rx to Tx 350...

Page 12: ...p VIC VOD pp tf 80 20 VOD U 0 0V Differential 100 tPLH VOC tr VOD O VOC SS VB Vswing tPLH Vcc V Vcc 0 2 V DC Coupled AC Coupled Figure 5 2 Timing Test Circuit and Definitions Zo RT Zo RT TMDS Driver T...

Page 13: ...ential Skew Figure 5 4 TMDS Outputs Control Timing Definitions S1 Clocking S2 A B A B A B 75mV 75mV HI Z 75mV 75mV tsx ten Y Z Output 2 VDD 0V VDD tsx tdis Port 1 Port 2 Port 3 Vcc 0 4 V Vcc V Vcc 0 4...

Page 14: ...0V 2 Vcc tpdHLRT DDC tpdLHRT DDC HPD_SINK HPD1 HPD2 HPD3 S1 S2 SDA_SINK SDA1 SDA2 SDA3 VDD 1 5V tSX DDC 1 5V VDD 0V tpdHLTR DDC tpdLHTR DDC tfTX DDC trTX DDC tfRX DDC trRX DDC 80 20 80 20 RX to TX TX...

Page 15: ...output Buffer AVCC power down controler VCC BU16028KV Low Vsat TR Tx side need more than 10mA load VCC 10k GND 3pin HPD2 Figure 6 1 Ist mode application 2 HPD_SINK Pull down resistance HPD_SINK is a 5...

Page 16: ...MI sw input like following application There is possibility that 1080p 12bit image isn t displayed It s depend on receiver IC characteristic When system is required 1080p 12bit Rohm doesn t recommend...

Page 17: ...12 0 0 2 10 0 0 1 12 0 0 2 0 145 0 5 0 15 0 1 0 05 1 4 0 05 1 25 1 25 1 0 0 2 1 6Max 0 05 0 04 0 2 0 5 0 1 4 6 4 0 05 0 03 0 08 S 0 08 M When you order please order in times the amount of package qua...

Page 18: ...this document are no antiradiation design Appendix1 Rev2 0 Thank you for your accessing to ROHM product informations More detail product informations and catalogs are available please contact your nea...

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