BU1570KN, BU1571KN
Technical Note
5/8
www.rohm.com
2009.04- Rev.B
© 2009 ROHM Co., Ltd. All rights reserved.
●
Timing Chart
1.
Two-line serial interface
1.1 Two-line serial interface timing
Table 1.1-1
I
2
C Interface timing
2.
Camera module interface
2.1. Camera module interface timing
The input timing of camera image signal on camera I/F is shown in Table 2.1-1.
The input timing of camera image signal on camera I/F is shown in Table 2.1-2.
Symbol
Explanation
MIN
TYP
MAX.
UNIT
t
PCLK
Clock Cycle
19.
-
-
ns
d
PCLK
Clock Duty
45
50
55
%
t
PDV
Decision of CAMDO from CAMCKO
-
-
5
ns
t
PHL,
t
PHH
Decision of CAMVSO or CAMHSO from CAMCKO
-
-
5
ns
Symbol Parameter MIN.
TYP.
MAX.
Unit
f
SCL
SDC Clock Frequency
0
-
400
kHz
t
HD;STA
Hold-time(repetition)
『
START
』
conditions
(The first clock pulse is generated after this period.)
0.6 - - us
f
LOW
The "L" period of SDC clock
1.3
-
-
us
t
HIGH
The "H" period of SDC clock
0.6
-
-
us
t
SU;STA
Setup time of repetitive
『
START
』
conditions
0.6 - - us
t
HD;DAT
Hold time of SDA
0
-
us
t
SU;DAT
Setup time of SDA
100
-
-
ns
t
SU;STO
Setup time of the
『
STOP
』
conditions
0.6 - - us
t
BUF
BUS free time between
『
STOP
』
conditions and the
『
START
』
conditions
1.3 - - us
Symbo
Explanation
MIN
TYP
MAX.
UNIT
tCMS
CAMCKI Rise / Fall Camera set-up Time
4
-
-
ns
tCMH
CAMCKI Rise / Fall Camera Hold Time
4
-
-
ns
t
LOW
SDA
SDC
t
HD;STA
t
HD;DAT
t
HIGH
t
SU;DAT
t
SU;STA
t
HD;ST
t
SU;STO
t
BUF
Table
2.1-1
BU1570KN/BU1571KN timing (Camera data input)
Table 2.1-2
Camera data output timing
CAMVSI
CAMHSI
CAMDI0
－
CAMDI7
CAMCKI
(CKPOL=“1”)
CAMCKI
(CKPOL=“0”)
tCMS
tCMH
CAMVSO
CAMDO[7:0]
CAMHSO
CAMCKO
tPCLK
tPHH
tPHL
tPDV
