Rohde & Schwarz SML01, Operating Manual

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R&S®SML / R&S®SMV03 Status Reporting System
1090.3123.12 E-6 5.17
CONDition part The CONDition part is directly written to by the hardware or the sum bit of the
next lower register. Its contents reflects the current instrument status. This
register part can be read only but not written to or cleared. Reading does not
affect it contents.
PTRansition part The Positive Transition part acts as an edge detector. If a bit of the CONDition
part changes from 0 to 1, the status of the associated PTR bit determines
whether the EVENt bit is set to 1.
PTR bit = 1: the EVENt bit is set.
PTR bit = 0: the EVENt bit is not set.
This part can be written to and read. Reading does not affect its contents.
NTRansition part The Negative Transition part likewise acts as an edge detector. If a bit of the
CONDition part changes from 1 to 0, the status of the associated NTR bit
determines whether the EVENt bit is set to 1.
NTR bit = 1: the EVENt bit is set.
NTR bit = 0: the EVENt bit is not set.
This part can be written to and read. Reading does not affect its contents.
With the above two edge register parts, the user can define what status
transition of the CONDition part (none, 0 to 1, 1 to 0 or both) is to be stored in
the EVENt part.
EVENt part The EVENt part indicates whether an event has occurred since it was read the
last time; it is the "memory" of the CONDition part. It indicates only those
events that were passed on by the edge filters. The EVENt part is continuously
updated by the instrument. This part can be read only. Upon reading, its
contents is set to zero. In linguistic usage, the EVENt part is often treated as
equivalent to the complete register.
ENABle part The ENABle part determines whether the associated EVENt bit contributes to
the sum bit (see below). Each bit of the EVENt part is ANDed with the
associated ENABle bit (symbol '&'). The results of all logical operations of this
part are passed on to the sum bit via an OR function (symbol '+').
ENABle-Bit = 0: the associated EVENt bit does not contribute to the sum bit.
ENABle-Bit = 1: if the associated EVENT bit is "1", the sum bit is set to "1"
as well.
This part can be written to and read. Reading does not affect its contents.
Sum bit As mentioned above, the sum bit is obtained from the EVENt part and the
ENABle part for each register. The result is entered as a bit of the CONDition
part into the next higher register.
The instrument automatically generates a sum bit for each register. It is thus
ensured that an event, for example a PLL that has not locked, can produce a
service request throughout all hierarchical levels.
Note: The service request enable (SRE) register defined in IEEE 488.2 can be taken as the
ENABle part of the STB if the STB is structured in accordance with SCPI. Analogously, the
ESE can be taken as the ENABle part of the ESR.