PIO Port Bit
Pin #
STi5519 Alternate Function
CineMaster CE Function
Port 0 Bit 0
Port 0 Bit 1
Port 0 Bit 2
Port 0 Bit 3
Port 0 Bit 4
Port 0 Bit 5
Port 0 Bit 6
Port 0 Bit 7
186
187
188
189
190
191
192
193
SC0_DATA
#ATAPI_RD
#ATAPI_WR
SC0_CLK
SC0_RST
SC0_CMD_VCC
SC0_DATA_DIR
SC0_DETECT
#SOFT_RESET
#ATAPI_RD
#ATAPI_WR
DAC_CCLK (Audio DAC control)
DAC_CDTI (Audio DAC control)
#DAC_CS0 (Audio DAC control)
#DAC_CS1 (Audio DAC control)
Unused (Test Point 39)
Port 1 Bit 0
Port 1 Bit 1
Port 1 Bit 2
Port 1 Bit 3
Port 1 Bit 4
Port 1 Bit 5
Port 1 Bit 6
Port 1 Bit 7
194
195
196
197
200
201
202
203
SSC0_DATA
SSC0_CLK
PARA_DVALID/SC_EXT_CLK
TXD2
RXD2
PARA_SYNC/TXD1
TRIGIN
TRIGOUT
SDA (I2C)
SCL (I2C)
Unused (Test Point 35)
TXD (Serial Port)
RXD (Serial Port)
SR0 (for PLL1700)
TRIGIN (JTAG)
TRIGOUT (JTAG)
Port 2 Bit 0
Port 2 Bit 1
Port 2 Bit 2
Port 2 Bit 3
Port 2 Bit 4
Port 2 Bit 5
Port 2 Bit 6
Port 2 Bit 7
204
205
206
207
208
1
2
3
SC1_DATA
PARA_REQ/RXD1
PARA_STR
SC1_CLK
SC1_RST
SC1_CMD_VCC
DAC_DATA/SC1_DATA_DIR
SC1_DETECT
FPCLK (Front Panel)
FS0 (for PLL1700)
FS1 (for PLL1700)
RTS (Serial Port)
CTS (Serial Port)
FPDATA (Front Panel)
DAC_DATA (Stereo Audio)
FPSTRB (Front Panel)
Port 3 Bit 0
Port 3 Bit 1
Port 3 Bit 2
Port 3 Bit 3
Port 3 Bit 4
Port 3 Bit 5
Port 3 Bit 6
Port 3 Bit 7
6
7
8
9
10
11
12
13
PARA_DATA0
PARA_DATA1
PARA_DATA2
PARA_DATA3
PARA_DATA4
PARA_DATA5
PARA_DATA6/COMP1
PARA_DATA7/COMP2
OPEN (TMM Tray Control)
CLOSE (TMM Tray Control)
Unused (Test Point 36)
Front Panel IR
Unused (Test Point 37)
Unused (Test Point 38)
#SENSE (TMM Tray Control)
#PUSH (TMM Tray Control)
Port 4 Bit 0
Port 4 Bit 1
Port 4 Bit 2
Port 4 Bit 3
Port 4 Bit 4
Port 4 Bit 5
Port 4 Bit 6
Port 4 Bit 7
39
40
41
42
43
44
45
46
YUV0
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
YUV0 (External Video DENC)
YUV1
YUV2
YUV3
YUV4
YUV5
YUV6
YUV7
* Front Panel uses the 16311 controller. In the CineMaster design, FPDIN and FPDOUT are connected
together as FPDATA.
