1. GENERAL DESCRIPTION
Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the
document.
1.1 STi5519
The STi5519 provides a highly integrated back-end solution for DVD applications. A host CPU handles
both the general application (the user interface, and the DVD, CD-DA, VCD, SVCD navigation) and the
drivers of the different embedded peripheral (audio/video, sub-picture decoders, OSD,
PAL/NTSC encoder...)
These functions include:
Integrated 32-bit host CPU @ 60MHz
- 2 Kbytes of instruction cache, 2 Kbytes of data cache, and 4Kbytes of SRAM configurable as
data cache.
Audio decoder
- 5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs
- IEC60958 - IEC61937 digital output
- DTS® digital out 5.1 channel
- SRS®/TruSurround®
- MP3 decoding
Video decoder
- Supports MPEG-2 MP@ML
- Fully programmable zoom-in and zoom-out
- PAL to NTSC and NTSC to PAL conversion
DVD and SVCD subpicture decoder
High performance on-screen display
- to 8 bits per pixel OSD options
- Anti-flicker, anti-flutter and anti-aliasing filters
PAL/NTSC/SECAM encoder
- RGB, CVBS, Y/C and YUV outputs with 10-bit DACs
- Macrovision® 7.01/6.1 compatible
Shared SDRAM memory interface
- Supports one or two 16Mbit, or one 64Mbit 125 MHZ SDRAMs
Programmable CPU memory interface for SDRAM, ROM, peripherals...
Front-end interface
- DVD, VCD, SVCD and CD-DA compatible
- Serial, parallel and ATAPI interfaces
- Hardware sector filtering
- Integrated CSS decryption and track buffer
Integrated peripherals
- UARTS, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers
- Modem support
- 38 bits of programmable I/O
Please refer to the STi5519 Data Sheets: STi5519 DVD HOST PROCESSOR WITH ENHANCED
AUDIO FEATURES and STi5519 REGISTER MANUAL for more detailed information.
1.2 MEMORY
The STi5519 includes all of the interface signals to connect to industry standard SDRAM, DRAM, ROM, and I2C
memory devices. The system includes one or two SDRAM components. The MPEG decoder unit interfaces to a single
4M x 16bit SDRAM over the SMI bus. The general purpose processor can share the decoder SDRAM or can access
an optional SDRAM installed on the EMI bus. This EMI SDRAM can be either a 1Mx16 or 4Mx16 chip. The optional
EMI SDRAM can be installed if the system requires higher performance of requires more RAM than is standard
system (due to complex trick modes, advanced GUI, etc). The standard production executes without EMI SDRAM
