RT7285C
13
DS7285C-03 July 2014
www.richtek.com
©
Copyright 2014 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
P
D(MAX)
= (T
J(MAX)
−
T
A
) /
θ
JA
where T
J(MAX)
is the maximum junction temperature, T
A
is
the ambient temperature, and
θ
JA
is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125
°
C. The junction to
ambient thermal resistance,
θ
JA
, is layout dependent. For
SOT-23-6 / TSOT-23-6 package, the thermal resistance,
θ
JA
, is 160
°
C/W on a standard four-layer thermal test board.
The maximum power dissipation at T
A
= 25
°
C can be
calculated by the following formula :
P
D(MAX)
= (125
°
C
−
25
°
C) / (160
°
C/W) = 0.625W for
SOT-23-6 / TSOT-23-6 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T
J(MAX)
and thermal
resistance,
θ
JA
. The derating curve in Figure 7 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Figure 7. Derating Curve of Maximum Power Dissipation
Layout Considerations
For best performance of the RT7285C, the following layout
guidelines must be strictly followed.
Input capacitor must be placed as close to the IC as
possible.
SW should be connected to inductor by wide and short
trace. Keep sensitive components away from this trace.
0.0
0.4
0.8
1.2
1.6
2.0
0
25
50
75
100
125
Ambient Temperature (°C)
Ma
xi
mu
m P
o
w
e
r Di
ss
ip
a
tio
n
(
W
)
1
Four-Layer PCB
Figure 8. PCB Layout Guide
BOOT
GND
FB
SW
VIN
EN
4
2
3
5
6
SW
V
OUT
R1
R2
V
IN
C
IN
C
IN
C
S*
R
S*
R
EN
C
OUT
C
OUT
SW should be connected to inductor by Wide and
short trace. Keep sensitive components away from
this trace. Suggestion layout trace wider for thermal.
Keep sensitive components away
from this trace. Suggestion layout
trace wider for thermal.
Suggestion layout trace
wider for thermal.
The feedback components must be
connected as close to the device as
possible.
The R
EN
component must
be connected to V
IN
.
Suggestion layout trace
wider for thermal.
Input capacitor must be placed as close
to the IC as possible. Suggestion layout
trace wider for thermal.
V
OUT
GND
