DNT500
2008 by RF Monolithics,
Inc.
33
M-0500-0000 Rev D
for instance in applications where a wireless link is replacing an RS-485 serial bus. When
this setting is one, in transparent mode the base will direct packets to the last remote that
registered with it. This is useful for point-to-point networks where there are only two
endpoints, for instance in applications where a simple serial cable is being replaced.
4.2.6 Bank 5 - I/O Peripheral Registers
Size in Range
Bank Loc'n
Name
R/W bytes in bits Default
05 00
GPIO0 R/W 1 1
0
05 01
GPIO1 R/W 1 1
0
05 02
GPIO2 R/W 1 1
0
05 03
GPIO3 R/W 1 1
0
05 04
GPIO2 R/W 1 1
0
05 05
GPIO3 R/W 1 1
0
05 06
ADC0 R 2
10
N/A
05 07
ADC1 R 2
10
N/A
05 08
ADC2 R 2
10
N/A
05 09
PWM0 R/W
2 9
0
05 0A
PWM1 R/W
2 9
0
GPIO0..5
Writing to these registers sets the corresponding driver for pins that are enabled outputs.
Writing to pins that are enabled as inputs enables or disables the internal pull-up. Reading
these registers returns the current level detected on the corresponding pin.
ADC0..2
Read-only, returns the current 10-bit ADC reading for the selected register. See the dis-
cussion of the ADC_SampleIntvl parameter below.
PWM0..1
Sets the PWM (DAC) outputs. The DC voltage derived from the integrated low-pass fil-
ters on the PWM output provides and effective DAC resolution of 8 bits. The range of
this parameter is 0x0000 to 0x0100.
4.2.7 Bank 6 - I/O setup
Size in Range
Bank Loc'n
Name
R/W bytes in
bits Default;
Options
06
00
GPIO_Dir
R/W
1 4
0 (all inputs)
06
01
GPIO_Init
R/W
1 4
0 (all zeros)
06
02
GPIO_Alt
R/W
1 4
0x08 = use GPIO3 for RS485 enable
06 03
GPIO_MessageMode R/W
1 8
GPIO messages disabled
06 04
GPIO_SleepMode
R/W
1 1
0 = off; 1 = use sleep I/O states
06 05
GPIO_SleepDDR
R/W
1 6
0 (all inputs)
06 06
GPIO_SleepState
R/W
1 6
0 (all zeros)
06 07
PWMA_Init
R/W
2 10
0x0000
06 09
PWMB_Init
R/W
2 10
0x0000
06 0B
ADC_SampleIntvl
R/W
2 16
0x0001 (10 ms)
06 0D
ADC0 ThresholdLo R/W
2 10
0x0000