RF-BM-2652P3
Shenzhen RF-star Technology Co., Ltd.
Page 4 of 20
1 Device Overview
1.1 Description
RF-BM-2652P3 is an RF module based on TI lower-power CC2652P SoC, which is a multiprotocol 2.4 GHz wireless
module supporting Thread, Zigbee
®
, Bluetooth
®
5.1 Low Energy, IEEE 802.15.4, IPv6-enabled smart objects
(6LoWPAN), proprietary systems, including the TI 15.4-Stack (2.4 GHz), and concurrent multiprotocol through a
Dynamic Multiprotocol Manager (DMM) driver. It integrates a 48 MHz crystal and a 32.768 kHz crystal, 352 KB of
in-system Programmable Flash and an external flash of 1 MB, 256 KB ROM,
8 KB of Cache SRAM, 80 KB of ultra-low
leakage SRAM. Its ARM
®
Cortex
®
-M4F core application processor can operate at an extremely low current at flexible
power modes. And the module enables long-range and low-power applications using inte20 dBm high-power
amplifier with best-in-class transmit current consumption at 85 mA. It features small size, robust connection distance,
and rigid reliability.
1.2 Key Features
•
RF Section
- 2.4GHz RF transceiver compatible with Bluetooth
5.1 Low Energy and earlier LE specifications and
IEEE 802.15.4 PHY and MAC
- Excellent receiver sensitivity
-100 dBm for 802.15.4 (2.4 GHz)
-105 dBm for Bluetooth 125 kbps (LE coded
PHY)
- Output power up to +20 dBm with temperature
compensation
- Suitable for systems targeting compliance with
worldwide radio frequency regulations
•
Wireless Protocols
- Thread, ZigBee
®
,
Bluetooth
®
5.1 Low Energy, IEEE
802.15.4, IPv6-nabld smart objects (6LoWPAN),
Wi-SUN
®
,
Proprietary
systems,
SimpleLink
TM
TI15.4-Stack (2.4 GHz), and Dynamic Multiprotocol
Manager (DDM) driver
•
Microcontroller
- Powerful 48 MHz ARM
®
Cortex
®
-M4F processor
- EEBMC CoreMark
®
score: 148
- 352 KB of in-system programmable flash + 1
MB flash
- 256 KB of ROM for protocols and library
functions
- 8 KB of cache SRAM (Alternatively available as
general-purpose RAM)
- 80 KB of ultra-low leakage SRAM. The SRAM is
protected by parity to ensure high reliability of
operation.
- 2-pin cJTAG and JTAG debugging
- Support OTA upgrade
•
Ultra-low power sensor controller with 4 KB of
SRAM
- Sample, store, and process sensor data
- Operation independent from system CPU
- Fast wake-up for low-power operation
•
Peripherals
- Digital peripheral pins can be routed to 23
GPIOs
- 4 × 32-bit or 8 × 16-bit general-purpose timers
- 12-bit ADC, 200 ksamples/s, 8 channels
- 2 × comparators with internal reference DAC (1
× continuous time, 1 × ultra-low power)
- Programmable current source
- 2 × UART
- 2 × SSI (SPI, Microwave, TI)
- I
2
C
