Emulation Adapter
Names and Functions of Hardware
R20UT5180EJ0110 Rev. 1.10
Page 9 of 63
Sep.12.22
(12) Jumper block: JP9 (FLMD1)
JP9 (FLMD1)
Specification
Open-circuit
Setting prohibited.
1-2 short-circuit
The FLMD1 pin for the debug chip is controlled by the emulator (CN1 connector
for external tracing).
2-3 short-circuit
(default)
The FLMD1 pin for the debug chip is controlled by the target system.
(13) Jumper block: JP13 (FLMD1_SEL)
JP13 (FLMD1_SEL)
Specification
Open-circuit
Setting prohibited.
1-2 short-circuit
(default)
The FLMD1 pin for the debug chip is controlled by the emulator (CN1 connector
for external tracing).
2-3 short-circuit
Setting prohibited.
(14) Jumper block: JP15 (RES_SEL)
JP15 (RES_SEL)
Specification
Open-circuit
Setting prohibited.
1-2 short-circuit
(default)
The RESET pin for the debug chip is controlled by the emulator (CN1 connector
for external tracing).
2-3 short-circuit
Setting prohibited.
(15) Jumper block: JP1 (VDD_EMU)
JP1 (VDD_EMU)
Specification
Open-circuit
When the SYSVCC power for the debug chip is 2.5 V or more, the VDD power or
EMUVDD power is generated from the emulation adapter.
Short-circuit
(default)
When the PWRCTL pin for the debug chip is high, the VDD power or EMUVDD
power is generated from the emulation adapter.
When the PWRCTL pin for the debug chip is in the high-impedance state and the
SYSVCC power is 2.5 V or more, the VDD power or EMUVDD power is generated
from the emulation adapter.
(16) Jumper block: JP4 (EMUVDD)
JP4 (EMUVDD)
Specification
Open-circuit
Setting prohibited.
1-2 short-circuit
(default)
When the PWRCTL pin for the debug chip is high or the SYSVCC power is 2.5
V or more, the EMUVDD power is generated from the emulation adapter.
This specification depends on the settings of JP1.
2-3 short-circuit
The EMUVDD power is always generated from the emulation adapter.
