CHAPTER 14 SERIAL ARRAY UNIT
Page 344 of 920
14.3.9
Serial channel stop register m (STm)
The STm register is a trigger register that is used to enable stopping communication/count by each channel.
When 1 is written a bit of this register (STmn), the corresponding bit (SEmn) of serial channel enable status
register m (SEm) is cleared to 0 (operation is stopped). Because the STmn bit is a trigger bit, it is cleared
immediately when SEmn = 0.
The STm register can set written by a 16-bit memory manipulation instruction.
The lower 8 bits of the STm register can be set with a 1-bit or 8-bit memory manipulation instruction with STmL.
Reset signal generation clears the STm register to 0000H.
Figure 14 - 15 Format of Serial channel stop register m (STm)
Note
Holding status value of the control register and shift register, the SCKmn and SOmn pins, and FEFmn,
PEFmn, OVFmn flags.
Caution
Be sure to clear bits 15 to 4, 1, and 0 of the ST0 register, and bits 15 to 4 of the ST1 register to “0”.
Remark
When the STm register is read, 0000H is always read.
After reset: 0000H
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
ST03 ST02
0
0
After reset: 0000H
Symbol
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
ST13 ST12 ST11 ST10
STm
n
Operation stop trigger of channel n
0
No trigger operation
1
Clears the SEmn bit to 0 and stops the communication operation
.
Summary of Contents for RL78/G1H
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