CHAPTER 8 TIMER RJ
Page 234 of 920
8.5
Cautions for Timer RJ
8.5.1
Count Operation Start and Stop Control
• When the count source is set to other than the ELC
After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF
bit in the TRJCR0 register remains 0 (count stops) for three cycles of the count source. Do not access the
registers associated with timer RJ
other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for three
cycles of the count source. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with timer RJ
other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TATART bit from 0 to 1. Refer to
for details.
Note
Registers associated with timer RJ: TRJ0, TRJCR0, and TRJMR0
• When the count source is set to the ELC
After 1 (count starts) is written to the TSTART bit in the TRJCR0 register while the count is stopped, the TCSTF
bit in the TRJCR0 register remains 0 (count stops) for two cycles of the CPU clock. Do not access the registers
associated with timer RJ
other than the TCSTF bit until this bit is set to 1 (count in progress).
After 0 (count stops) is written to the TSTART bit during a count operation, the TCSTF bit remains 1 for two
cycles of the CPU clock. When the TCSTF bit is set to 0, the count is stopped. Do not access the registers
associated with timer RJ
other than the TCSTF bit until this bit is set to 0.
Clear the interrupt register before changing the TATART bit from 0 to 1. Refer to
for details.
Note
Registers associated with timer RJ: TRJ0, TRJCR0, and TRJMR0
8.5.2
Access to Flags (TUNDF bit in TRJCR0 Register)
Bit TUNDF in the TRJCR0 register are set to 0 by writing 0 by a program, but writing 1 to these bits has no effect.
If a read-modify-write instruction is used to set the TRJCR0 register, bit TUNDF may be erroneously set to 0
depending on the timing, even when the TUNDF bit is set to 1 (underflow) during execution of the instruction.
Use an 8-bit memory manipulation instruction to access to the TRJCR0 register.
8.5.3
Access to Counter Register
When bits TSTART and TCSTF in the TRJCR0 register are both 1 (count starts), allow at least three cycles of the
count source clock between writes when writing to the TRJ0 register successively.
8.5.4
When Changing Mode
The register associated with timer RJ operating mode (TRJMR0) can be changed only
when the count is stopped with both the TSTART and TCSTF bits set to 0 (count stops). Do not change these
registers during count operation.
When the registers associated with timer RJ operating mode are changed, the value of TUNDF bit is undefined.
Write 0 (no underflow) to the TUNDF bit before starting the count.
Summary of Contents for RL78/G1H
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