R-CAR V3M Starter Kit
R12UT0003ED0230 Rev 2.30
Page 17 of 54
January 24, 2019
Under development
Preliminary document
Specifications in this document are tentative and subject to change.
2. SoC Mode
The SoC mode is configured by using dedicated GPIO pins on the SoC. These pins are driven by a CPLD which is the
responsible to set up the GPIOs during reset.
The CPLD contains a register where the SoC mode configuration is stored. Some of the configuration bits of the SoC
register are accessible through the DIP switch 4 (SW4) available on the board. The rest of the bits have a default value.
The preset values are shown in the Table 4. It is possible to write the CPLD register via proprietary CPLD interface or from
PC with the GUI provided by Renesas. The SoC is also connected to the CPLD interface and can modify the SoC mode
register if it is necessary.
Figure 5. CPLD and SW4 multiplexing diagram
.
The CPLD contains a multiplexer to select the Boot Mode configuration source either from the SW4 or from the internal
register. This should be defined with the GUI under the tab “SOC mode configuration” and then selecting the desired option
on the “MODE setting” checkbox as shown in the figure 4.
REG
M
U
X
Reset
CPLD
R-Car V3M
PC
SW4
Reset
Reset
Mode
Pins
MDxx
Summary of Contents for R-Car V3M
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