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Rev.2.00 Nov 28, 2005 page 289 of 378
REJ09B0124-0200

M16C/6N Group (M16C/6NK, M16C/6NM)

21. Flash Memory Version

Under development

This document is under development and its contents are subject to change.

Figure 21.17 Pin Connections for CAN I/O Mode (1)

CNVSS

RESET

CTX

CRX

VSS

VCC1

VCC2

SCLK

EPM

M16C/6N Group (M16C/6NK)

(Flash memory version)

Connect

oscillator

circuit

CNVSS

EPM

RESET

SCLK

TXD

Signal

Mode setup method

Value

VCC1

VSS

VSS to VCC1

VCC2

VSS

VCC1

Package: PLQP0100KB-A

TXD

2 3

4 5

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

100

Summary of Contents for M16C/6NK

Page 1: ...MILY M16C 60 SERIES 16 Rev 2 00 Revision date Nov 28 2005 Hardware Manual www renesas com Before using this material please visit our website to verify that this is the most updated document available...

Page 2: ...here may contain technical inaccuracies or typographical errors Renesas Technology Corporation assumes no responsibility for any damage liability or other loss rising from these inaccuracies or error...

Page 3: ...to the bit concerned As the bit may be use for future functions set to 0 when writing to this bit Do not set to this value The operation is not guaranteed when a value is set Function varies dependin...

Page 4: ...ng charts Software Manual Detailed description of assembly instructions and microcomputer performance of each instruction Application Note Application examples of peripheral functions Sample programs...

Page 5: ...lag 17 2 8 2 Debug Flag D Flag 17 2 8 3 Zero Flag Z Flag 17 2 8 4 Sign Flag S Flag 17 2 8 5 Register Bank Select Flag B Flag 17 2 8 6 Overflow Flag O Flag 17 2 8 7 Interrupt Enable Flag I Flag 17 2 8...

Page 6: ...e 69 8 4 2 Wait Mode 71 8 4 3 Stop Mode 73 8 5 Oscillation Stop and Re oscillation Detection Function 78 8 5 1 Operation When CM27 Bit 0 Oscillation Stop Detection Reset 78 8 5 2 Operation When CM27 B...

Page 7: ...RDY Signal 108 12 2 DMA Transfer Cycles 110 12 3 DMA Enable 111 12 4 DMA Request 111 12 5 Channel Priority and DMA Transfer Timing 112 13 Timers 113 13 1 Timer A 115 13 1 1 Timer Mode 119 13 1 2 Even...

Page 8: ...eptance Mask Registers 224 19 1 3 CAN SFR Registers 224 19 2 CANi Message Box 225 19 3 Acceptance Mask Registers 227 19 4 CAN SFR Registers 228 19 5 Operational Modes 234 19 5 1 CAN Reset Initializati...

Page 9: ...e of Circuit Application in Standard Serial I O Mode 286 21 5 Parallel I O Mode 287 21 5 1 User ROM and Boot ROM Areas 287 21 5 2 ROM Code Protect Function 287 21 6 CAN I O Mode 288 21 6 1 ID Code Che...

Page 10: ...Functions to Prevent Flash Memory from Rewriting 371 23 19 2 Stop Mode 371 23 19 3 Wait Mode 371 23 19 4 Low Power Dissipation Mode and On Chip Oscillator Low Power Dissipation Mode 371 23 19 5 Writi...

Page 11: ...0h 0071h 0072h 0073h 0074h 0075h 0076h 0077h 0078h 0079h 007Ah 007Bh 007Ch 007Dh 007Eh 007Fh CAN0 1 Wake up Interrupt Control Register CAN0 Successful Reception Interrupt Control Register CAN0 Success...

Page 12: ...CAN0 Message Box 5 Identifier DLC CAN0 Message Box 5 Data Field CAN0 Message Box 5 Time Stamp 225 226 Address Register Symbol Page 00C0h 00C1h 00C2h 00C3h 00C4h 00C5h 00C6h 00C7h 00C8h 00C9h 00CAh 00C...

Page 13: ...age Box 12 Data Field CAN0 Message Box 12 Time Stamp CAN0 Message Box 13 Identifier DLC CAN0 Message Box 13 Data Field CAN0 Message Box 13 Time Stamp 225 226 C0GMR C0LMAR C0LMBR Address Register Symbo...

Page 14: ...1 Register Timer A2 1 Register Timer A4 1 Register Three Phase PWM Control Register 0 Three Phase PWM Control Register 1 Three Phase Output Buffer Register 0 Three Phase Output Buffer Register 1 Dead...

Page 15: ...Error Count Register CAN0 Transmit Error Count Register CAN0 Time Stamp Register CAN1 Message Control Register 0 CAN1 Message Control Register 1 CAN1 Message Control Register 2 CAN1 Message Control R...

Page 16: ...CAN1 Message Box 5 Identifier DLC CAN1 Message Box 5 Data Field CAN1 Message Box 5 Time Stamp 225 226 Address Register Symbol Page 02C0h 02C1h 02C2h 02C3h 02C4h 02C5h 02C6h 02C7h 02C8h 02C9h 02CAh 02C...

Page 17: ...age Box 12 Data Field CAN1 Message Box 12 Time Stamp CAN1 Message Box 13 Identifier DLC CAN1 Message Box 13 Data Field CAN1 Message Box 13 Time Stamp 225 226 C1GMR C1LMAR C1LMBR Address Register Symbo...

Page 18: ...3 146 144 154 153 153 154 155 153 154 153 153 154 155 153 156 105 106 221 221 146 123 146 123 123 146 116 119 121 126 128 131 133 134 136 Address Register Symbol Page AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A...

Page 19: ...high level of instruction efficiency With 1 Mbyte of address space they are capable of executing instructions at high speed Being equipped with two CAN Controller Area Network modules in M16C 6N Group...

Page 20: ...r 15 bits 1 channel with prescaler Interrupt Internal 32 sources External 9 sources Software 4 sources Priority level 7 levels Clock Generating Circuit 4 circuits Main clock oscillation circuit Sub cl...

Page 21: ...34 sources External 12 sources Software 4 sources Priority level 7 levels Clock Generating Circuit 4 circuits Main clock oscillation circuit Sub clock oscillation circuit On chip oscillator PLL frequ...

Page 22: ...16 bits Output timer A 5 Input timer B 6 Three phase motor control circuit Internal peripheral functions Watchdog timer 15 bits A D converter 10 bits 8 channels Expandable up to 26 channels UART or C...

Page 23: ...AN module pin count etc 6N Group M16C Family Type No ROM Capacity RAM Capacity Package Type Remarks M306NKFHGP 384 K 4 Kbytes 31 Kbytes PLQP0100KB A Flash Normal ver M306NMFHGP PLQP0128KB A memory M30...

Page 24: ...P2_3 AN2_3 A3 D3 D2 P2_4 AN2_4 A4 D4 D3 P2_5 AN2_5 A5 D5 D4 P2_6 AN2_6 A6 D6 D5 P2_7 AN2_7 A7 D7 D6 P3_0 A8 D7 P3_1 A9 P3_2 A10 P3_3 A11 P3_4 A12 P3_5 A13 P3_6 A14 P3_7 A15 P4_0 A16 P4_1 A17 P4_2 A18...

Page 25: ...___ TA4IN U 20 P8_0 TA4OUT U SIN4 21 P7_7 TA3IN CRX1 22 P7_6 TA3OUT CTX1 23 P7_5 ____ TA2IN W SOUT4 24 P7_4 TA2OUT W CLK4 25 P7_3 ___ TA1IN V __________ __________ CTS2 RTS2 26 P7_2 TA1OUT V CLK2 27 P...

Page 26: ..._3 AN2_3 A3 D3 D2 68 P2_2 AN2_2 A2 D2 D1 69 P2_1 AN2_1 A1 D1 D0 70 P2_0 AN2_0 A0 D0 71 P1_7 _________ INT5 D15 72 P1_6 _________ INT4 D14 73 P1_5 _________ INT3 D13 74 P1_4 D12 75 P1_3 D11 76 P1_2 D10...

Page 27: ...D3 D2 P2_4 AN2_4 A4 D4 D3 P2_5 AN2_5 A5 D5 D4 P2_6 AN2_6 A6 D6 D5 P2_7 AN2_7 A7 D7 D6 P3_0 A8 D7 P3_1 A9 P3_2 A10 P3_3 A11 P3_4 A12 P3_5 A13 P3_6 A14 P3_7 A15 P4_0 A16 P4_1 A17 P4_2 A18 P4_3 A19 P4_4...

Page 28: ..._____ RESET 18 XOUT 19 VSS 20 XIN 21 VCC1 22 P8_5 ________ NMI 23 P8_4 _________ INT2 ZP 24 P8_3 _________ INT1 25 P8_2 _________ INT0 26 P8_1 ___ TA4IN U 27 P8_0 TA4OUT U SIN4 28 P7_7 TA3IN CRX1 29 P...

Page 29: ...3 P12_6 64 P12_5 65 P4_7 _______ CS3 66 P4_6 _______ CS2 67 P4_5 _______ CS1 68 P4_4 _______ CS0 69 P4_3 A19 70 P4_2 A18 71 P4_1 A17 72 P4_0 A16 73 P3_7 A15 74 P3_6 A14 75 P3_5 A13 76 P3_4 A12 77 P3_3...

Page 30: ...104 P0_7 AN0_7 D7 105 P0_6 AN0_6 D6 106 P0_5 AN0_5 D5 107 P0_4 AN0_4 D4 108 P0_3 AN0_3 D3 109 P0_2 AN0_2 D2 110 P0_1 AN0_1 D1 111 P0_0 AN0_0 D0 112 P11_7 SIN6 113 P11_6 SOUT6 114 P11_5 CLK6 115 P11_4...

Page 31: ...us Output address bits A0 to A19 Input and output data D0 to D7 and output address bits A0 to A7 by time sharing when external 8 bit data bus are set as the multiplexed bus Input and output data D0 to...

Page 32: ...lock from XCIN and leave XCOUT open Outputs the BCLK signal The clock of the same cycle as fC f8 or f32 is output ______ Input pins for the INT interrupt _______ Input pin for the NMI interrupt Input...

Page 33: ...t for a pull up or for no pull up in 4 bit unit by program however P7_1 and P9_1 for the N channel open drain output _______ Input pin for the NMI interrupt Pin states can be read by the P8_5 bit in t...

Page 34: ...tic logic operations A1 is the same as A0 In some instructions A1 and A0 can be combined for use as a 32 bit address register A1A0 2 Central Processing Unit CPU Figure 2 1 shows the CPU registers The...

Page 35: ...al use it must be set to 0 2 8 3 Zero Flag Z Flag This flag is set to 1 when an arithmetic operation resulted in 0 otherwise it is 0 2 8 4 Sign Flag S Flag This flag is set to 1 when an arithmetic ope...

Page 36: ...is allocated to the addresses from FFE00h to FFFDBh This vector is used by the JMPS or JSRS instruction For details refer to M16C 60 M16C 20 M16C Tiny Series Software Manual In memory expansion and m...

Page 37: ...Control Register Address Match Interrupt Register 0 Address Match Interrupt Register 1 Chip Select Expansion Control Register 4 PLL Control Register 0 Processor Mode Register 2 DMA0 Source Pointer DMA...

Page 38: ...er SI O5 Interrupt Control Register 1 Timer B4 Interrupt Control Register UART1 Bus Collision Detection Interrupt Control Register Timer B3 Interrupt Control Register UART0 Bus Collision Detection Int...

Page 39: ...B2h 00B3h 00B4h 00B5h 00B6h 00B7h 00B8h 00B9h 00BAh 00BBh 00BCh 00BDh 00BEh 00BFh CAN0 Message Box 2 Identifier DLC CAN0 Message Box 2 Data Field CAN0 Message Box 2 Time Stamp CAN0 Message Box 3 Ident...

Page 40: ...F2h 00F3h 00F4h 00F5h 00F6h 00F7h 00F8h 00F9h 00FAh 00FBh 00FCh 00FDh 00FEh 00FFh CAN0 Message Box 6 Identifier DLC CAN0 Message Box 6 Data Field CAN0 Message Box 6 Time Stamp CAN0 Message Box 7 Ident...

Page 41: ...33h 0134h 0135h 0136h 0137h 0138h 0139h 013Ah 013Bh 013Ch 013Dh 013Eh 013Fh CAN0 Message Box 10 Identifier DLC CAN0 Message Box 10 Data Field CAN0 Message Box 10 Time Stamp CAN0 Message Box 11 Identif...

Page 42: ...161h 0162h 0163h 0164h 0165h 0166h 0167h 0168h 0169h 016Ah 016Bh 016Ch 016Dh 016Eh 016Fh 0170h 0171h 0172h 0173h 0174h 0175h 0176h 0177h 0178h 0179h 017Ah 017Bh 017Ch 017Dh 017Eh 017Fh CAN0 Message Bo...

Page 43: ...4h 0185h 0186h 0187h 0188h 0189h 018Ah 018Bh 018Ch 018Dh 018Eh 018Fh 0190h 0191h 0192h 0193h 0194h 0195h 0196h 0197h 0198h 0199h 019Ah 019Bh 019Ch 019Dh 019Eh 019Fh 01A0h 01A1h 01A2h 01A3h 01A4h 01A5h...

Page 44: ...de Register 4 UART2 Special Mode Register 3 UART2 Special Mode Register 2 UART2 Special Mode Register UART2 Transmit Receive Mode Register UART2 Bit Rate Generator UART2 Transmit Buffer Register UART2...

Page 45: ...ister CAN0 Time Stamp Register CAN1 Message Control Register 0 CAN1 Message Control Register 1 CAN1 Message Control Register 2 CAN1 Message Control Register 3 CAN1 Message Control Register 4 CAN1 Mess...

Page 46: ...ripheral Clock Select Register CAN0 1 Clock Select Register CAN1 Message Box 0 Identifier DLC CAN1 Message Box 0 Data Field CAN1 Message Box 0 Time Stamp CAN1 Message Box 1 Identifier DLC CAN1 Message...

Page 47: ...2B2h 02B3h 02B4h 02B5h 02B6h 02B7h 02B8h 02B9h 02BAh 02BBh 02BCh 02BDh 02BEh 02BFh CAN1 Message Box 2 Identifier DLC CAN1 Message Box 2 Data Field CAN1 Message Box 2 Time Stamp CAN1 Message Box 3 Iden...

Page 48: ...2F2h 02F3h 02F4h 02F5h 02F6h 02F7h 02F8h 02F9h 02FAh 02FBh 02FCh 02FDh 02FEh 02FFh CAN1 Message Box 6 Identifier DLC CAN1 Message Box 6 Data Field CAN1 Message Box 6 Time Stamp CAN1 Message Box 7 Iden...

Page 49: ...333h 0334h 0335h 0336h 0337h 0338h 0339h 033Ah 033Bh 033Ch 033Dh 033Eh 033Fh CAN1 Message Box 10 Identifier DLC CAN1 Message Box 10 Data Field CAN1 Message Box 10 Time Stamp CAN1 Message Box 11 Identi...

Page 50: ...0361h 0362h 0363h 0364h 0365h 0366h 0367h 0368h 0369h 036Ah 036Bh 036Ch 036Dh 036Eh 036Fh 0370h 0371h 0372h 0373h 0374h 0375h 0376h 0377h 0378h 0379h 037Ah 037Bh 037Ch 037Dh 037Eh 037Fh CAN1 Message B...

Page 51: ...ode Register Timer A2 Mode Register Timer A3 Mode Register Timer A4 Mode Register Timer B0 Mode Register Timer B1 Mode Register Timer B2 Mode Register Timer B2 Special Mode Register UART0 Transmit Rec...

Page 52: ...tion Register Port P10 Register Port P11 Register 1 Port P10 Direction Register Port P11 Direction Register 1 Port P12 Register 1 Port P13 Register 1 Port P12 Direction Register 1 Port P13 Direction R...

Page 53: ...gram in an address indicated by the reset vector The internal RAM is not reset When an L signal is applied to the ____________ RESET pin while writing data to the internal RAM the internal RAM is in a...

Page 54: ...t port ______ WR output H is output ______ WR output H is output P5_1 Input port ________ BHE output undefined ________ BHE output undefined P5_2 Input port ______ RD output H is output ______ RD outp...

Page 55: ...ter SFR for details Processor mode remains unchanged since the PM01 to PM00 bits in the PM0 register are not reset 5 3 Watchdog Timer Reset The microcomputer resets pins the CPU and SFR when the PM12...

Page 56: ...ssor modes Table 6 1 Features of Processor Modes Processor Mode Access Space Pins Which are Assigned I O Ports Single chip Mode SFR internal RAM internal ROM All pins are I O ports or peripheral funct...

Page 57: ...ailable in T V ver Do not set a value Table 6 3 PM01 to PM00 Bits Set Values and Processor Modes NOTE 1 Not available in T V ver Do not set a value Rewriting the PM01 to PM00 bits places the microcomp...

Page 58: ...fter reset If the PM05 to PM04 bits are set to 11b during memory expansion mode P3_1 to P3_7 and P4_0 to P4_3 become I O ports in which case the accessible area for each CS is 256 bytes Not available...

Page 59: ...b memory expansion mode or 11b microprocessor mode Not available memory expansion and microprocessor modes in T V ver This bit is reserved bit in T V ver and set to 0 4 The PM12 bit is set to 1 by wri...

Page 60: ...512 Kbytes Address YYYYYh D0000h D0000h D0000h D0000h Internal RAM PM13 bit in PM1 register 0 1 PM13 bit 1 Internal ROM Capacity 16 Kbytes 20 Kbytes 31 Kbytes Address XXXXXh 043FFh 053FFh 07FFFh Capac...

Page 61: ...AM 16 Kbytes 20 Kbytes 03FFFh 03FFFh 31 Kbytes 03FFFh Address YYYYYh 1 Capacity Internal ROM 192 Kbytes 256 Kbytes D0000h D0000h 384 Kbytes 512 Kbytes D0000h D0000h _____ Figure 6 4 Memory Map and CS...

Page 62: ...pacity Internal RAM 16 Kbytes 20 Kbytes 03FFFh 03FFFh 31 Kbytes 03FFFh Address YYYYYh 1 Capacity Internal ROM 192 Kbytes 256 Kbytes D0000h D0000h 384 Kbytes 512 Kbytes D0000h D0000h _____ Figure 6 6 M...

Page 63: ...multiplexed 7 1 2 2 When the input level on BYTE pin is low 16 bit data bus D0 to D7 and A1 to A8 are multiplexed D8 to D15 are not multiplexed Do not use D8 to D15 External devices connecting to a mu...

Page 64: ...PM06 0 A16 to A19 NOTE 1 No values other than those shown above can be set 7 2 1 Address Bus The address bus consists of 20 lines A0 to A19 The address bus width can be chosen to be 12 16 or 20 bits b...

Page 65: ...al area indicated by CSi The chip select signal changes state but the address bus does not change state Example 1 BCLK Read signal Data bus Address bus CSi Access to the external area indicated by CSi...

Page 66: ...ess when the ALE signal falls Figure 7 3 shows the ALE signal address bus and data bus Figure 7 3 ALE Signal Address Bus Data Bus L H L H L H L H Data Bus Width _____ RD ________ WRL _________ WRH Sta...

Page 67: ...ded for accessing external devices which need to be accessed at low speed If input on ________ the RDY pin is asserted low at the last falling edge of BCLK of the bus cycle one wait state is inserted...

Page 68: ...he CPU is accessing an odd address in word units the DMAC cannot gain control of the bus during two separate accesses Figure 7 5 Bus using Priorities Table 7 5 Microcomputer Status in Hold State NOTES...

Page 69: ...0 0 I O ports CS0 1 _______ CS0 P4_5 CS1 0 I O ports CS1 1 _______ CS1 P4_6 CS2 0 I O ports CS2 1 _______ CS2 P4_7 CS3 0 I O ports CS3 1 _______ CS3 P5_0 PM02 0 _______ WR PM02 1 3 ________ WRL 3 ____...

Page 70: ...A0 to A19 Address output Maintain status before accessed address of external area or SFR D0 to D15 When read High impedance High impedance When write Output data Undefined _____ ______ ________ ______...

Page 71: ...Bits CS01W to CS00W Bits NOTES 1 ________ To use the RDY signal set this bit to 0 2 To access in multiplexed bus mode set the corresponding bit of CS0W to CS3W to 0 with wait state 3 After reset the P...

Page 72: ...ength After this bus cycle sometimes come read and write cycles in succession Output Input Address Address BCLK Read signal Write signal Data bus Address bus CS 2 Separate bus 1 wait setting BCLK Read...

Page 73: ...3 wait setting Address bus Data bus Address Address Data output Address Address Input ALE BCLK CS Write signal Read signal Address bus 2 Multiplexed bus 1 or 2 wait setting Address Data output Addres...

Page 74: ...ons Item Main Clock Oscillation Circuit Sub Clock Oscillation Circuit On chip Oscillator PLL Frequency Synthesizer Use of Clock Clock Frequency Usable Oscillator Pins to Connect Oscillator Oscillation...

Page 75: ...uest level judgment output 1 2 1 2 1 2 1 2 1 2 Details of divider b 1 8 1 4 1 2 a 1 32 CM06 0 CM17 CM16 11b CM06 0 CM17 CM16 10b CM06 1 CM06 0 CM17 CM16 01b CM06 0 CM17 CM16 00b PM00 PM01 Bits in PM0...

Page 76: ...all to 0 7 When the CM21 bit 0 on chip oscillator turned off and the CM05 bit 1 main clock turned off the CM06 bit is fixed to 1 divide by 8 mode and the CM15 bit is fixed to 1 drive capability High 8...

Page 77: ...setting the PRC0 bit in the PRCR register to 1 write enable 2 If the CM10 bit is 1 stop mode XOUT goes H and the internal feedback resistor is disconnected The XCIN and XCOUT pins are placed in the h...

Page 78: ...detected 6 If the CM20 bit is 1 and the CM23 bit is 1 main clock turned off do not set the CM21 bit to 0 7 Effective when the CM07 bit in the CM0 register is 0 8 Where the CM20 bit is 1 oscillation st...

Page 79: ...register Address 004Eh is changed from the ADIC KUPIC register to the ADIC register 3 When this bit 1 the A D clock is set to divide by 1 of fAD mode regardless of whether the PCLK0 bit is set 4 When...

Page 80: ...owing conditions The on chip oscillator starts oscillating and the on chip oscillator clock becomes the watchdog timer count source The CM10 bit in the CM1 register is disabled against write Writing a...

Page 81: ...C01 PLC02 b3 b4 b6 b5 Reserved Bit Set to 1 Reserved Bit Set to 0 PLL Multiplying Factor Select Bit 2 RW RW RW RW RW RW Nothing is assigned When write set to 0 When read its content is indeterminate N...

Page 82: ...the CM0 register to 1 main clock oscillator circuit turned off after switching the clock source for the CPU clock to a sub clock or on chip oscillator clock In this case XOUT goes H Furthermore becaus...

Page 83: ...rated clock to the XCIN pin Figure 8 10 shows the examples of sub clock connection circuit After reset the sub clock is turned off At this time the feedback resistor is disconnected from the oscilla t...

Page 84: ...clock source for the CPU and peripheral function clocks After reset the PLL clock is turned off The PLL frequency synthe sizer is activated by setting the PLC07 bit to 1 PLL operation When the PLL cl...

Page 85: ...LC00 bits multiplying factor When PLL clock 16 MHz Set the PM20 bit to 0 2 wait state Set the PLC07 bit to 1 PLL operation Set the CM11 bit to 1 PLL clock for the CPU clock source END Using the PLL cl...

Page 86: ...cillator low power dissipation mode or when the CM05 bit in the CM0 register is set to 1 main clock turned off in low speed mode the CM06 bit in the CM0 register is set to 1 divide by 8 mode NOTE 1 No...

Page 87: ...main clock change the operation mode to the medium speed mode divide by 8 mode after the clock was divided by 8 the CM06 bit in the CM0 register was set to 1 in the on chip oscillator mode 8 4 1 1 Hi...

Page 88: ...lock source for the peripheral function clocks If the sub clock is activated fC32 can be used as the count source for timers A and B Table 8 3 lists the setting clock related bit and modes Table 8 3 S...

Page 89: ...during wait mode Table 8 4 Pin Status During Wait Mode NOTES 1 Not available memory expansion and microprocessor modes in T V ver 2 Not available the bus control pins in T V ver 8 4 2 4 Exiting Wait...

Page 90: ...used in CAN sleep mode Can be used in CAN sleep mode If the microcomputer is to be moved out of wait mode by a peripheral function interrupt set up the following before executing the WAIT instruction...

Page 91: ...p re oscillation detection function disabled Also if the CM11 bit in the CM1 register is 1 PLL clock for the CPU clock source set the CM11 bit to 0 main clock for the CPU clock source and the PLC07 bi...

Page 92: ...it stop mode must have larger value than that of the RLVL2 to RLVL0 bits The ILVL2 to ILVL0 bits in all other interrupt control registers for the peripheral function interrupts which are not used to e...

Page 93: ...and CM1 registers per 16 bits with the CM21 bit in the CM2 register 0 on chip oscillator stops Since the operation starts from the main clock after exiting stop mode the time until the CPU operates ca...

Page 94: ...register become effective when the PLC07 bit is set to 1 PLL on Change the PM20 bit when the PLC07 bit is set to 0 PLL off Set the PM20 bit to 0 2 waits when PLL clock 16 MHz PM20 bit to 0 SFR access...

Page 95: ...6 1 7 CM06 1 CPU clock divide by 8 mode 8 CM07 0 Main clock PLL clock or on chip oscillator clock selected 9 CM07 1 Sub clock selected 10 CM05 0 Main clock oscillating 11 CM05 1 Main clock turned off...

Page 96: ...illation stop reset refer to 4 Special Function Register SFR 5 Reset This status is reset with hardware reset Also even when re oscillation is detected the microcomputer can be initialized and stopped...

Page 97: ...ion detection interrupt request is generated At the same time the on chip oscillator starts oscillating In this case although the CPU clock is derived from the sub clock as it was before the interrupt...

Page 98: ...ting the PRC2 bit to 1 Make sure no interrupts or DMA transfers will occur between the instruction in which the PRC2 bit is set to 1 and the next instruction The PRC0 and PRC1 bits are not automatical...

Page 99: ...r whose interrupt priority cannot be changed by priority level Interrupt Software Non maskable interrupt Hardware Special Non maskable interrupt Peripheral function 1 Maskable interrupt Undefined inst...

Page 100: ...BS ADC ADCF ADD CMP DIV DIVU DIVX NEG RMPA SBB SHA SUB 10 2 3 BRK Interrupt A BRK interrupt occurs when executing the BRK instruction 10 2 4 INT Instruction Interrupt An INT instruction interrupt occu...

Page 101: ...Oscillation Stop and Re oscillation Detection Interrupt Generated by the oscillation stop and re oscillation detection function For details about the oscillation stop and re oscillation detection fun...

Page 102: ...0 0 0 0 MSB LSB High order address Interrupt Source Vector table Addresses Reference Address L to Address H Undefined Instruction UND instruction FFFDCh to FFFDFh M16C 60 M16C 20 M16C Tiny Overflow IN...

Page 103: ...13 Timers 10 6 INT Interrupt 13 Timers ______ 10 6 INT Interrupt M16C 60 M16C 20 16C Tiny Series Software Manual Interrupt Source Vector Address 1 Address L to Address H Reference NOTES 1 Address rela...

Page 104: ...the interrupt request for that register For details refer to 23 8 Interrupt 2 Use the IFSR07 bit in the IFSR0 register to select 3 Use the IFSR06 bit in the IFSR0 register to select 4 This bit can onl...

Page 105: ...memory expansion or microprocessor mode set the ILVL2 to ILVL0 bits in the INT5IC to INT3IC registers to 000b interrupt disabled Not available memory expansion and microprocessor modes in T V ver 3 Th...

Page 106: ...settings of interrupt priority levels and Table 10 4 shows the interrupt priority levels enabled by the IPL The following are conditions under which an interrupt is accepted I flag 1 IR bit 1 interru...

Page 107: ...r to an interrupt sequence is saved to a temporary register 1 within the CPU 3 The I D and U flags in the FLG register become as follows The I flag is set to 0 interrupt disabled The D flag is set to...

Page 108: ...om when an interrupt request is generated till when the instruction then executing is completed a on Figure 10 6 and a time during which the interrupt sequence is executed b on Figure 10 6 Interrupt S...

Page 109: ...to 63 has been executed this is the SP indicated by the U flag Otherwise it is the ISP m 4 m 3 m 2 m 1 m m 1 SP SP value before interrupt request is accepted Stack status before interrupt request is...

Page 110: ...errupt request is generated or not the interrupt request that has the highest priority is accepted For maskable interrupts peripheral functions interrupt any desired priority level can be selected usi...

Page 111: ...0 INT2 INT0 INT3 Timer B5 SI O5 2 Interrupt request level resolution output to clock generating circuit Figure 8 1 Clock Generating Circuit Interrupt request accepted IPL I Flag DBC NMI CAN1 Successfu...

Page 112: ...____ ________ A2 INT8 share with Timer B1 To use the INT4 to INT8 interrupts 1 set the each bits as follows ________ ________ To use the INT4 interrupt Set the IFSR16 bit in the IFSR1 register to 1 IN...

Page 113: ...1 SI O5 The SI O5 interrupt is only in the 128 pin version In the 100 pin version set the IFSR04 bit to 0 Timer B5 6 Timer B0 and SI O6 share the vector and interrupt control register When using the...

Page 114: ...rrupt control register When using CAN1 successful transmission or SI O3 interrupt set the IFSR16 bit to 0 CAN1 successful transmission SI O3 When using INT4 interrupt set the IFSR16 bit to 1 INT4 Duri...

Page 115: ...n version make sure the INT6 to INT8 interrupt polarity switching bitis set to 0 falling edge 2 Timer A2 and INT7 share the vector and interrupt control register When using the timer A2 interrupt set...

Page 116: ...pt Note however that while input on any pin which has had the PD10_4 to PD10_7 bits set to 0 input mode is pulled low inputs on all other pins of the port are not detected as interrupts Interrupt cont...

Page 117: ...e of the PC that is saved to the stack area when an address match interrupt request is accepted Table 10 7 shows the relationship between address match interrupt sources and associated registers Note...

Page 118: ...3 b2 b1 b0 RW Address Match Interrupt Enable Register 2 Address Match Interrupt 2 Enable Bit Address Match Interrupt 3 Enable Bit 0 Interrupt disabled 1 Interrupt enabled 0 Interrupt disabled 1 Interr...

Page 119: ...can be calculated as given below The period of watchdog timer is however subject to an error due to the prescaler For example when CPU clock 16 MHz and the divide by n value for the prescaler 16 the...

Page 120: ...er watchdog timer starts counting Setting the PM22 bit to 1 results in the following conditions The on chip oscillator starts oscillating and the on chip oscillator clock becomes the watchdog timer co...

Page 121: ...MS and DSEL3 to DSEL0 bits in the DMiSL register However unlike in the case of interrupt requests DMA requests are not affected by the I flag and the interrupt control register so that even when inter...

Page 122: ...e DMAi transfer counter underflows after reaching the terminal count Repeat Transfer When the DMAi transfer counter underflows it is reloaded with the value of the DMAi transfer counter reload registe...

Page 123: ...L0 bits are 0001b software trigger The value of this bit when read is 0 DMA Request Cause Expansion Select Bit 0 Basic cause of request 1 Extended cause of request See NOTE 1 RW RW RW RW RW RW RW NOTE...

Page 124: ...uest DMS 1 extended cause of request Falling edge of INT1 pin Software trigger Timer A0 Timer A1 Timer A2 Timer A3 SI O3 Timer A4 Timer B0 Two edges of INT1 pin Timer B1 Timer B2 UART0 transmit SI O4...

Page 125: ...transfer counter reload register and when the DMAE bit in the DMiCON register is set to 1 DMA enabled or the DMAi transfer counter underflows when the DMASL bit in the DMiCON register is 1 repeat tra...

Page 126: ...transferred on an 8 bit data bus input on the BYTE pin high the operation is accomplished by transferring 8 bits of data twice Therefore this operation requires two bus cycles to read data and two bu...

Page 127: ...e 2 When the transfer unit is 16 bits and the source address of transfer is an odd address or when the transfer unit is 16 bits and an 8 bit bus is used BCLK Address bus RD signal WR signal Data bus C...

Page 128: ...Depends on the set value of the CSE register 3 Not available external area in T V ver This condition does not exist NOTE 1 Not available memory expansion and microprocessor modes in T V ver Table 12 3...

Page 129: ...with the DMS and DSEL3 to DSEL0 bits in the DMiSL register i 0 1 on either channel Table 12 4 shows the timing at which the DMAS bit changes state Whenever a DMA request is generated the DMAS bit is...

Page 130: ...g priority is received first to start a transfer when a DMA0 request and DMA1 request are generated simultaneously After one DMA0 transfer is completed a bus arbitration is returned to the CPU When th...

Page 131: ...NSF register or TRGSR register NOTE 1 Be aware that TA0IN shares the pin with RXD2 SCL2 and TB5IN TCK1 to TCK0 10 01 00 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 TA0TGH to TA0TGL...

Page 132: ...00 01 10 11 TCK1 TMOD1 to TMOD0 00 Timer mode 10 Pulse width period measuring mode 01 Event counter mode TCK1 to TCK0 1 0 00 01 10 11 TCK1 TMOD1 to TMOD0 00 Timer mode 10 Pulse width period measuring...

Page 133: ...in ONSF register If i 0 bits in TRGSR register if i 1 to 4 TAiS Bit in TABSR register TAiUD Bit in UDF register i 0 to 4 j i 1except j 4 when i 0 k i 1 except k 0 when i 4 NOTE 1 Overflow or underflow...

Page 134: ...idth n fj where n set value fj count source frequency NOTES 1 The register must be accessed in 16 bit unit 2 The timer counts pulses from an external device or overflows or underflows in other timers...

Page 135: ...n the TAiMR register to 0 switching source in UDF register during event counter mode 0 Two phase pulse signal processing disabled 1 Two phase pulse signal processing enabled 2 3 Symbol Address After R...

Page 136: ...TA4OS TA0TGL TA0TGH TAZIE Symbol Address After Reset TRGSR 0383h 00h Timer A1 Event Trigger Select Bit Trigger Select Register Bit Name Function Bit Symbol b7 b6 b5 b4 b3 b2 b1 b0 Timer A2 Event Trigg...

Page 137: ...lect Function Gate function Counting can be started and stopped by an input signal to TAiIN pin Pulse output function Whenever the timer underflows the output polarity of TAiOUT pin is inverted When T...

Page 138: ...and until the 1st count source is input after counting start Value written to the TAi register is written to both reload register and counter When counting after 1st count source input Value written t...

Page 139: ...MR3 Set to 0 in event counter mode TCK0 Count Operation Type Select Bit 0 1 0 0 Counts falling edge of external signal 1 Counts rising edge of external signal Up Down Switching Cause Select Bit 0 UDF...

Page 140: ...er is written to both reload register and counter When counting after 1st count source input Value written to TAi register is written to reload register Transferred to counter when reloaded next Selec...

Page 141: ...t 1 2 0 Reload type 1 Free run type 0 Normal processing operation 1 Multiply by 4 processing operation 0 0 1 RW RW RW RW RW RW RW RW To use two phase pulse signal processing set this bit to 0 To use t...

Page 142: ...detecting Z phase input edge The active edge can be selected to be the rising or falling edge by using the POL bit in the INT2IC register The Z phase pulse width ________ applied to the INT2 pin must...

Page 143: ...er reaching 0000h TAiS bit is set to 0 stop counting Interrupt Request Generation Timing When the counter reaches 0000h TAiIN Pin Function I O port or trigger input TAiOUT Pin Function I O port or pul...

Page 144: ...a pulse output pin MR2 MR1 MR3 Set to 0 in one shot timer mode 0 0 f1 or f2 0 1 f8 1 0 f32 1 1 fC32 b7 b6 TCK1 TCK0 Count Source Select Bit 1 0 0 0 TAiOS bit is enabled 1 Selected by TAiTGH to TAiTGL...

Page 145: ...th n fj n set value of the TAi register Cycle time 216 1 fj fixed fj count source frequency f1 f2 f8 f32 fC32 8 bit PWM High level width n m 1 fj n set value of the TAi register high order address Cyc...

Page 146: ...0 Count Source Select Bit 16 8 Bit PWM Mode Select Bit Trigger Select Bit External Trigger Select Bit 1 RW RW RW RW RW 1 Selected by TAiTGH to TAiTGL bits 0 Falling edge of input signal to TAiIN pin 2...

Page 147: ...d by the TAiTGH and TAiTGL bits 1 fj n Set to 0 upon accepting an interrupt request or by writing in program Count source 1 Input signal to TAiIN pin Underflow signal of 8 bit prescaler 2 PWM pulse ou...

Page 148: ...e timer measures pulse period or pulse width of an external signal TCK1 to TCK0 TMOD1 to TMOD0 Bits in TBiMR register TBiS Bit in TABSR register or TBSR register i 0 to 5 j i 1 except j 2 when i 0 j 5...

Page 149: ...t Symbol Address After Reset TB0MR to TB2MR 039Bh to 039Dh 00XX0000b TB3MR to TB5MR 01DBh to 01DDh 00XX0000b NOTES 1 Timer B0 timer B3 2 Timer B1 timer B2 timer B4 timer B5 Symbol Address After Reset...

Page 150: ...TB1S TB0S TA4S TA3S TA2S TA1S TA0S Function RW RW RW RW RW RW RW RW RW Symbol Address After Reset TBSR 01C0h 000XXXXXb Timer B3 B4 B5 Count Start Flag b7 b6 b5 b4 b3 b2 b1 b0 Bit Name Bit Symbol Timer...

Page 151: ...ister Transferred to counter when reloaded next 13 2 1 Timer Mode In timer mode the timer counts a count source generated internally Table 13 6 lists specifications in timer mode Figure 13 18 shows TB...

Page 152: ...ows TBiMR register in event counter mode Table 13 7 Specifications in Event Counter Mode Figure 13 19 TB0MR to TB5MR Registers in Event Counter Mode Timer Bi Mode Register i 0 to 5 Symbol Bit Name Fun...

Page 153: ...t Read from Timer Contents of the reload register measurement result can be read by reading TBi register 3 Write to Timer Value written to the TBi register is written to neither reload register nor co...

Page 154: ...ured pulse and between a rising edge and the next falling edge 1 1 Do not set a value Function b3 b2 Count Source Select Bit Timer Bi Overflow Flag 1 0 Timer did not overflow 1 Timer has overflown 0 0...

Page 155: ...bit 5 to bit 7 in the TABSR register and the TB3S to TB5S bits are assigned to bit 5 to bit 7 in the TBSR register Set to 0 upon accepting an interrupt request or by writing in program Measurement pul...

Page 156: ...r Wave Cycle Triangular wave modulation count source m 1 2 Sawtooth wave modulation count source m 1 m Setting value of the TB2 register 0000h to FFFFh Count source f1 f2 f8 f32 fC32 Three Phase PWM O...

Page 157: ...1 Register TA1 Register TA11 Register Timer A4 Counter Timer A4 One Shot Pulse Timer A1 One Shot Pulse Timer A2 One Shot Pulse Reload Timer A1 Counter One Shot Timer Mode One Shot Timer Mode TA2 Regis...

Page 158: ...scribes how the INV06 bit works INV00 INV01 INV02 INV03 INV05 INV06 INV07 INV04 Function Three Phase PWM Control Register 0 1 Bit Name Bit Symbol Symbol Address After Reset INVC0 01C8h 00h RW RW RW RW...

Page 159: ...rite the INVC1 register after the PRC1 bit in the PRCR register is set to 1 write enable The timers A1 A2 A4 and B2 must be stopped during rewrite 2 The following table lists how the INV11 bit works 3...

Page 160: ...e output shift register by a transfer trigger After the transfer trigger occurs the values written in the IDB0 register determine each phase output signal first Then the value written in the IDB1 regi...

Page 161: ...VC1 register is set to 0 dead timer enabled phase switches from an inactive level to an active level when the dead time timer stops 5 When the INV11 bit in the INVC1 register is set to 0 three phase m...

Page 162: ...he INV00 bit is set to 1 the first interrupt is generated when the timer B2 underflows n 1 times n being the value set in the ICTB2 counter Subsequent interrupts are generated every n times the timer...

Page 163: ...01b TB2 underflow before using a W phase output control circuit Selects an input to the TA3IN pin 1 Selects TB2 2 Selects TA2 2 Selects TA4 2 Timer A3 Event Trigger Select Bit Timer A4 Event Trigger...

Page 164: ...ger Select Bit Trigger Select Bit Set to 0 with the three phase motor control timer function Count Source Select Bit b7 0 0 1 1 b6 0 1 0 1 Pulse Output Function Select Bit Set to 0 with the three phas...

Page 165: ...INV14 1 H active U phase U phase NOTES 1 Internal signals See Figure 14 1 Three Phase Motor Control Timer Functions Block Diagram 2 Applies only when the INV11 bit is set to 1 three phase mode Example...

Page 166: ...Transfer the counter to the three phase shift register Rewrite the IDB0 and IDB1 registers NOTES 1 Internal signals See Figure 14 1 Three Phase Motor Control Timer Functions Block Diagram The example...

Page 167: ...UART2 SI O3 to SI O6 15 1 UARTi i 0 to 2 UARTi each have an exclusive timer to generate a transfer clock so they operate independently of each other Figures 15 1 to 15 3 show the block diagram of UAR...

Page 168: ...the U0BRG register PCLK1 Bit in PCLKR register SMD2 to SMD0 CKDIR Bits in U0MR register CLK1 to CLK0 CKPOL CRD CRS Bits in U0C0 register RCSP Bit in UCON register Figure 15 2 UART1 Block Diagram RXD1...

Page 169: ...l RTS2 CTS2 TXD2 UART2 CLK polarity reversing circuit CLK1 to CLK0 00 01 10 CKDIR CKPOL UART reception UART transmission Clock synchronous type CKDIR 1 0 RXD polarity reversing circuit 0 1 VSS 0 1 SMD...

Page 170: ...8 bits Clock synchronous type UART 7 bits UART 9 bits Clock synchronous type UART 8 bits UART 9 bits UARTi receive register UiTB register UiRB register Data bus low order bits Data bus high order bit...

Page 171: ...MOV instruction to write to this register 3 Write to this register after setting the CLK1 to CLK0 bits in the UiC0 register Nothing is assigned When write set to 0 When read their contents are 0 b10...

Page 172: ...TS0 RTS0 not separated 2 Set the corresponding port direction bit for each CTSi pin to 0 input mode 3 SCL2 P7_1 is N channel open drain output The NCH bit in the U2C0 register is N channel open drain...

Page 173: ...TE TI RE Transmit Buffer Empty Flag Receive Enable Bit Transmit Enable Bit RI Receive Complete Flag 0 Transmission disabled 1 Transmission enabled 0 Data present in U2TB register 1 No data present in...

Page 174: ...RT1 CLK CLKS Select Bit 0 CLKMD0 Effective when the CLKMD1 bit 1 0 Clock output from CLK1 1 Clock output from CLKS1 RW NOTE 1 When using multiple transfer clock output pins make sure the following con...

Page 175: ...output by digital means during I2C mode In other than I2C mode set these bits to 000b no delay 2 The amount of delay varies with the load on SCLi and SDAi pins Also when using an external clock the am...

Page 176: ...1F4h 00h RW STAREQ RSTAREQ STPREQ Restart Condition Generate Bit 1 Stop Condition Generate Bit 1 Start Condition Generate Bit 1 STSPSEL SCL SDA Output Select Bit 0 Clear 1 Start 0 Clear 1 Start 0 Clea...

Page 177: ...UARTi transmit register at start of transmission The UiIRS bit 1 transfer completed when the serial I O finished sending data from the UARTi transmit register For reception When transferring data fro...

Page 178: ...enable transmission reception TI Transmit buffer empty flag RE Set this bit to 1 to enable reception RI Reception complete flag U2IRS 2 Select the source of UART2 transmit interrupt U2RRM 2 Set this b...

Page 179: ...of Selection Serial Data Output Serial Data Input Transfer Clock Output Transfer Clock Input ________ CTS Input ________ RTS Output I O Port Outputs dummy data when performing reception only PD6_2 and...

Page 180: ...TB register to the UARTi transmit register Make sure the following conditions are met when input to the CLKi pin before receiving data is high TE bit in UiC1 register 1 transmission enabled RE bit in...

Page 181: ...register to 001b clock synchronous serial I O mode 3 1 transmission enabled is written to the TE bit in the UiC1 register regardless of the TE bit 15 1 1 2 CLK Polarity Select Function Use the CKPOL b...

Page 182: ...s required when starting the operation mode When the UiRRM bit i 0 to 2 1 continuous receive mode the TI bit in the UiC1 register is set to 0 data present in UiTB register by reading the UiRB register...

Page 183: ...from the multiple pins function usage This function can be used when the selected transfer clock for UART1 is an internal clock Figure 15 15 Transfer Clock Output From Multiple Pins D0 D1 D2 D3 D4 D5...

Page 184: ...iC0 register 0 CTS function is selected ________ ________ _______ CTSi RTSi pin is CTS function _______ CRD bit 0 CRS bit 1 RTS function is selected ________ ________ _______ CTSi RTSi pin is RTS func...

Page 185: ...to the UiRB register at completion of reception Error Detection Overrun error 2 This error occurs if the serial I O started receiving the next data before reading the UiRB register and received the bi...

Page 186: ...e CTS or RTS function NCH Select TXDi pin output mode CKPOL Set to 0 UFORM LSB first or MSB first can be selected when transfer data is 8 bit long Set this bit to 0 when transfer data is 7 or 9 bit lo...

Page 187: ...election Serial Data Output Serial Data Input I O Port Transfer Clock Input _______ CTS Input ________ RTS Output I O Port Outputs H when performing reception only PD6_2 and PD6_6 bits in PD6 register...

Page 188: ...IR bit in SiTIC register Transferred from UiTB register to UARTi transmit register The above timing diagram applies to the case where the register bits are set as follows PRYE bit in UiMR register 1...

Page 189: ...ken in D7 D1 Transferred from UARTi receive register to UiRB register Figure 15 18 Receive Operation 15 1 2 1 Bit Rates In UART mode the frequency set by the UiBRG register i 0 to 2 divided by 16 beco...

Page 190: ...ed is written to the TE bit in the UiC1 register regardless of the TE bit 15 1 2 3 LSB First MSB First Select Function As shown in Figure 15 19 use the UFORM bit in the UiC0 register to select the tra...

Page 191: ...Di no reverse TXDi reverse SP ST D3 D4 D5 D6 D7 P D0 D1 D2 1 When the UiLCH bit in the UiC1 register 0 no reverse 2 When the UiLCH bit 1 reverse Transfer clock i 0 to 2 ST Start bit P Parity bit SP St...

Page 192: ...0 CTS function is selected ________ ________ _______ CTSi RTSi pin is CTS function _______ CRD bit 0 CRS bit 1 RTS function is selected ________ ________ _______ CTSi RTSi pin is RTS function _______...

Page 193: ...he CKDIR bit 1 external clock Input from SCLi pin Transmission Start Condition Before transmission can start the following requirements must be met 1 The TE bit in the UiC1 register 1 transmission ena...

Page 194: ...t request UARTi receive ACK interrupt request DMA1 request IICM 1 and IICM2 0 S R Q ALS R S SWC IICM 1 and IICM2 0 IICM2 1 IICM2 1 SWC2 SDHI DMA0 DMA1 request UART1 DMA0 only Noise Filter IICM 0 IICM...

Page 195: ...lock synchronization Set to 0 SWC Set this bit to 1 to have SCLi output fixed to L at the falling edge of the 9th bit of clock ALS Set this bit to 1 to have SDAi output Set to 0 stopped when arbitrati...

Page 196: ...rupt UART0 bus collision detection When using UART1 be sure to set the IFSR07 bit in the IFSR0 register to 1 cause of interrupt UART1 bus collision detection Function Clock Synchronous Serial I O Mode...

Page 197: ...register D6 D5 D4 D3 D2 D1 D7 SDAi SCLi D0 b15 b9 b8 b7 b0 1st bit 2nd bit 3rd bit 4th bit 5th bit 6th bit 7th bit 8th bit 9th bit 2 IICM2 0 CKPH 1 clock delay ACK interrupt DMA1 request NACK interrup...

Page 198: ...SMR register to determine which interrupt source is requesting the interrupt Figure 15 25 Detection of Start and Stop Condition 15 1 3 2 Output of Start and Stop Condition A start condition is generat...

Page 199: ...g the next byte Setting the ALS bit in the UiSMR2 register to 1 SDA output stop enabled causes arbitration lost to occur in which case the SDAi pin is placed in the high impedance state at the same ti...

Page 200: ...low level signal from the SCLi pin even while sending or receiving data Setting the SWC2 bit to 0 transfer clock allows the transfer clock to be output from or supplied to the SCLi pin instead of outp...

Page 201: ...Initialization of Transmission Reception If a start condition is detected while the STAC bit 1 UARTi initialization enabled the serial I O operates as described below The transmit shift register is in...

Page 202: ...1 transmission enabled The TI bit in the UiC1 register 0 data present in the UiTB register Interrupt Request For transmission one of the following conditions can be selected Generation Timing The UiI...

Page 203: ...elopment This document is under development and its contents are subject to change Figure 15 27 Serial Bus Communication Control Example UART2 Microcomputer Master Microcomputer Slave Microcomputer Sl...

Page 204: ...lock phases can be set in combination with the CKPH bit in the UiSMR3 register UFORM Set to 0 UiC1 TE Set this bit to 1 to enable transmission TI Transmit buffer empty flag RE Set this bit to 1 to ena...

Page 205: ...sfer clock polarity and phase are the same for the master and salves to be communicated Figure 15 28 shows the transmission and reception timing in master internal clock Figure 15 29 shows the transmi...

Page 206: ...ming CKPH 0 in Slave Mode External Clock Figure 15 30 Transmission and Reception Timing CKPH 1 in Slave Mode External Clock D0 D1 D2 D3 D4 D6 D7 D5 Indeterminate Slave control input Clock input CKPOL...

Page 207: ...id because the PRYE bit 0 PRYE Set to 0 IOPOL Select the TXD RXD input output polarity UiC0 CLK1 CLK0 Select the count source for the UiBRG register CRS Invalid because the CRD bit 1 TXEPT Transmit re...

Page 208: ...ing edge of RXDi when IOPOL bit 1 2 The transmit condition must be met before the falling edge 1 of RXDi 2 ACSE Bit in UiSMR Register auto clear of transmit enable bit TXDi RXDi ST D0 D1 D2 D3 D4 D5 D...

Page 209: ...stop bit of the next data Framing error 3 This error occurs when the number of stop bits set is not detected Parity error 3 During reception if a parity error is detected parity error signal is output...

Page 210: ...0 for inverse format PRYE Set to 1 IOPOL Set to 0 U2C0 CLK1 CLK0 Select the count source for the U2BRG register CRS Invalid because the CRD bit 1 TXEPT Transmit register empty flag CRD Set to 1 NCH S...

Page 211: ...level is detected by the interrupt routine The IR bit is set to 1 at the falling edge of transfer clock TC 16 n 1 fi or 16 n 1 fEXT fi frequency of U2BRG count source f1SIO f2SIO f8SIO f32SIO fEXT fre...

Page 212: ...a parity error signal the PER bit is set to 0 and at the same time the TXD2 output is returned high When transmitting a transmission finished interrupt request is generated at the falling edge of the...

Page 213: ...PRY bit in the U2MR register to 1 the UFORM bit in the U2C0 register to 0 and the U2LCH bit in the U2C1 register to 0 When inverse format set the PRY bit to 0 UFORM bit to 1 and U2LCH bit to 1 Figure...

Page 214: ...the specifications of SI Oi NOTE 1 100 pin version supports SI O3 and SI O4 128 pin version supports SI O3 SI O4 SI O5 and SI O6 Figure 15 36 SI Oi Block Diagram SiTRR register SI O counter i Synchron...

Page 215: ...SM32 SM52 or SM62 bit 1 the corresponding pin is placed in the high impedance state regardless of which functions of those pins are being used SI O4 is effective only when the SM43 bit 1 SOUT4 output...

Page 216: ...RF bits can only be reset by writing to 0 The S5TRF and S6TRF bits are only in the 128 pin version 2 When setting the S3TRF to S6TRF bits to 0 use the MOV instruction to write to the these bits after...

Page 217: ...ity selection Whether transmit data is output input timing at the rising edge or falling edge of transfer clock can be selected Table 15 19 SI Oi Specifications i 3 to 6 5 and 6 are only in the 128 pi...

Page 218: ...put SMi3 1 SOUTi output CLKi function SMi4 0 transmit data output at the falling edge and receive data input at the rising edge of the transfer clock SMi5 0 LSB first SMi6 1 internal clock NOTES 1 If...

Page 219: ...ter SOUTi internal SMi7 bit SOUTi output SMi3 bit Example When H selected for SOUTi initial value i 3 to 6 5 and 6 are only in the 128 pin version This diagram applies to the case where the bits in th...

Page 220: ...trigger retriggerable _____________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts Conversion Speed Per Pin Without sample and hold 8 bit r...

Page 221: ...er Software trigger 000b 001b 010b 011b 100b 101b 110b 111b 000b 001b 010b 011b 100b 101b 110b 111b CH2 to CH0 CH2 to CH0 AD0 register AD1 register AD2 register AD3 register AD4 register AD5 register...

Page 222: ...it Symbol Bit Name Function RW RW RW RW RW RW RW RW RW Bit name Function Bit symbol RW Symbol Address After Reset ADCON1 03D7h 00h 0 8 bit mode 1 10 bit mode 0 Any mode other than repeat sweep mode 1...

Page 223: ...2 2 0 Without sample and hold 1 With sample and hold 0 0 Port P10 group is selected 0 1 Do not set a value 1 0 Port P0 group is selected 1 1 Port P2 group is selected Set to 0 0 Selects fAD divide by...

Page 224: ...ADTRG trigger _____________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Completion of A D conversion If a software trigger...

Page 225: ...KS1 Bit Name Function Bit Symbol RW Symbol Address After Reset ADCON1 03D7h 00h 0 8 bit mode 1 10 bit mode Set to 0 when one shot mode is selected 1 VREF connected Refer to NOTE 2 for ADCON2 Register...

Page 226: ...e OPA1 to OPA0 bits in the ADCON1 register select a pin Analog voltage applied to this pin is repeatedly converted to a digital code A D Conversion When the TRG bit in the ADCON0 register is 0 softwar...

Page 227: ...10 Bit Mode Select Bit VREF Connect Bit 2 A D Operation Mode Select Bit 1 External Op Amp Connection Mode Bit Frequency Select Bit 1 0 0 ANEX0 and ANEX1 are not used 0 1 ANEX0 input is A D converted...

Page 228: ...ted one by one to a digital code A D Conversion When the TRG bit in the ADCON0 register is 0 software trigger Start Condition The ADST bit in the ADCON0 register is set to 1 A D conversion starts ____...

Page 229: ...3D7h 00h 0 8 bit mode 1 10 bit mode Set to 0 when single sweep mode is selected 1 VREF connected Refer to NOTE 2 for ADCON2 Register When single sweep mode is selected A D Sweep Pin Select Bit 8 10 Bi...

Page 230: ...ct pins Analog voltage applied to the pins is repeatedly converted to a digital code A D Conversion When the TRG bit in the ADCON0 register is 0 software trigger Start Condition The ADST bit in the AD...

Page 231: ...1 VREF connected Refer to NOTE 2 for ADCON2 Register When repeat sweep mode 0 is selected A D Sweep Pin Select Bit 8 10 Bit Mode Select Bit VREF Connect Bit 3 A D Operation Mode Select Bit 1 External...

Page 232: ...______ When the TRG bit is 1 ADTRG trigger _____________ Input on the ADTRG pin changes state from high to low after the ADST bit is set to 1 A D conversion starts A D Conversion Set the ADST bit to 0...

Page 233: ...W RW RW RW RW RW RW SCAN0 SCAN1 MD2 BITS VCUT OPA0 OPA1 CKS1 Bit Name Function Bit Symbol RW 0 8 bit mode 1 10 bit mode Set to 1 when repeat sweep mode 1 is selected 1 VREF connected Refer to NOTE 2 f...

Page 234: ...put pins Use the OPA1 to OPA0 bits in the ADCON1 register to select whether or not use ANEX0 and ANEX1 The A D conversion results of ANEX0 and ANEX1 inputs are stored in the AD0 and AD1 registers resp...

Page 235: ...time T sampling time as the specified time Let output impedance of sensor equivalent circuit be R0 microcomputer s internal resistance be R precision error of the A D converter be X and the resolution...

Page 236: ...Under development This document is under development and its contents are subject to change R0 R 7 8 k C 1 5 pF VIN Microcomputer Sensor equivalent circuit VC Sampling time Sample and hold enabled Sa...

Page 237: ...input mode Setting the DAiE bit to 1 removes a pull up from the corresponding port Output analog voltage V is determined by a set value n decimal in the DAi register V VREF n 256 n 0 to 255 VREF refer...

Page 238: ...bled Nothing is assigned When write set to 0 When read their contents are 0 NOTE 1 When not using the D A converter set the DAiE bit i 0 1 to 0 output disabled to reduce the unnecessary current consum...

Page 239: ...tion for one byte data is finished in two cycles Figure 18 1 shows the block diagram of the CRC circuit Figure 18 2 shows the CRC related registers Figure 18 3 shows the calculation example using the...

Page 240: ...Write 0000h initial value 3 Write 01h 4 Write 23h Details of CRC operation As shown in 3 above bit position of 01h 00000001b written to the CRCIN register is inversed and becomes 10000000b Add 1000 0...

Page 241: ...a field 8 bytes and a time stamp Acceptance filter This block performs filtering operation for received messages For the filtering operation the CiGMR register i 0 1 the CiLMAR register or the CiLMBR...

Page 242: ...l register j i 0 1 j 0 to 15 CiMCTLj register 8 bits 16 Control of transmission and reception of a corresponding slot CANi control register CiCTLR register 16 bits Control of the CAN protocol CANi sta...

Page 243: ...he number of the slot Address Message Content Memory mapping CAN0 CAN1 Byte access 8 bits Word access 16 bits 0060h n 16 0 0260h n 16 0 SID10 to SID6 SID5 to SID0 0060h n 16 1 0260h n 16 1 SID5 to SID...

Page 244: ...EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 DLC3 DLC2 DLC1 DLC0 CAN Data Frame SID10 to 6 SID5 to 0 EID17 to 14 EID13 to 6 EID5 to 0 DLC3 to 0 Data Byte 0 Data Byte 1 Data Byte...

Page 245: ...ID5 SID4 SID3 SID2 SID1 SID0 EID17 EID16 EID15 EID14 EID13 EID12 EID11 EID10 EID9 EID8 EID7 EID6 EID5 EID4 EID3 EID2 EID1 EID0 0160h 0161h 0162h 0163h 0164h 0166h 0167h 0168h 0169h 016Ah 016Ch 016Dh 0...

Page 246: ...Flag Remote Frame Transmission Reception Status Flag 2 0 Data frame transmission reception status 1 Remote frame transmission reception status RemActive RspLock Auto Response Lock Mode Select Bit Remo...

Page 247: ...abled 1 Loop back mode enabled 0 Bus error interrupt disabled 1 Bus error interrupt enabled 0 Sleep mode disabled 1 Sleep mode enabled clock supply stopped 0 I O port function 1 CTX CRX function b15 b...

Page 248: ...RO RO RO RO CANi Status Register i 0 1 NOTE 1 These bits can be changed only when a slot which an interrupt is enabled by the CiICR register is transmitted or received successfully b7 b6 b5 b4 b3 b2...

Page 249: ...ter Reset NOTE 1 This register can not be set in CAN reset initialization mode of the CAN module b15 b8 b7 b0 b7 b0 Function Interrupt enable bits Each bit corresponds with a slot with the same number...

Page 250: ...gment 2 Control Bits Resynchronization Jump Width Control Bits CANi Configuration Register i 0 1 b3 b2 b1 b0 b7 b6 b5 b2 b1b0 b5 b4 b3 b7 b6 NOTE 1 fCAN serves for the CAN clock The period is decided...

Page 251: ...error counting function The value is incremented or decremented according to the CAN module s error status 00h to FFh 1 CANi Transmit Error Count Register i 0 1 b7 b0 Function Counter Value RW RO C0TE...

Page 252: ...reset initialization mode is activated during an ongoing transmission in operation mode the module suspends the mode transition until completion of the transmission successful arbitration loss or err...

Page 253: ...e module receives a CAN message sent by another node Module transmits The module transmits a CAN message The module may receive its own message simultaneously when the LoopBack bit in the CiCTLR regis...

Page 254: ...the bus off state the module has the following two cases In this time the value of any CAN registers except CiSTR CiRECR and CiTECR registers does not change 1 When 11 consecutive recessive bits are...

Page 255: ...on the CAN bus the input comparator delay and the output driver delay Phase buffer segment 1 PBS1 This serves for compensating the phase error When the falling edge of the bit falls later than expect...

Page 256: ...one bit NOTES 1 fCAN division value 1 2 4 8 16 fCAN division value a value selected in the CCLKR register 2 Baud rate prescaler division value P 1 P 0 to 15 P a value selected in the BRP bit in the C...

Page 257: ...0 to 13 the CiLMAR register corresponds to slot 14 and the CiLMBR register corresponds to slot 15 The masking function becomes valid to 11 bits or 29 bits of a received ID according to the value in t...

Page 258: ...received ID The acceptance filter support unit can be used for the IDs of the standard frame only The acceptance filter support unit is valid in the following cases When the ID to receive cannot be m...

Page 259: ...ages are stored in slots 14 and 15 alternately Which type of message has been received can be checked by the RemActive bit in the CiMCTLj register Figure 19 19 shows the operation of slots 14 and 15 i...

Page 260: ...and Time Stamp Function When the CiTSR register i 0 1 is read the value of the time stamp counter at the moment is read The period of the time stamp counter reference clock is the same as that of 1 b...

Page 261: ...e the following points 1 Before configuring a slot as a transmission slot be sure to set the CiMCTLj registers to 00h 2 Set the TrmReq bit in the CiMCTLj register to 0 not transmission slot before rew...

Page 262: ...ge the NewData bit in the CiMCTLj register of the receiving slot becomes 1 stored new data in slot The InvalData bit in the CiMCTLj register becomes 1 message is being updated at the same time and the...

Page 263: ...the TrmState bit in the CiSTR register are set to 1 Transmitting Transmitter and CAN module starts the transmission 2 If the arbitration is lost after the CAN module starts the transmission the TrmAct...

Page 264: ...he following CAN interrupts CANi Successful Reception Interrupt i 0 1 CANi Successful Transmission Interrupt CAN0 1 Error Interrupt Error Passive State Error BusOff State Bus Error this feature can be...

Page 265: ...t a peripheral function input output pin or a bus control pin 1 For details on how to set peripheral functions refer to each functional description in this manual If any pin is used as a peripheral fu...

Page 266: ...be written to the port latch by writing to the Pi register The data written to the port latch is output from the pin The bits in the Pi register correspond one for one to each port During memory expa...

Page 267: ...Port latch Data bus Direction register Port latch Pull up selection Port P1 control register Data bus Direction register Port latch Pull up selection Port P1 control register Input to respective perip...

Page 268: ...to respective peripheral functions Switching between CMOS and Nch NOTE 1 Data bus Pull up selection Direction register Port latch Input to respective peripheral functions Data bus Pull up selection Di...

Page 269: ...Input to respective peripheral functions Switching between CMOS and Nch Output 1 Data bus Pull up selection Direction register Port latch Switching between CMOS and Nch Data bus NMI interrupt input Da...

Page 270: ...ion register Data bus Port latch Pull up selection Input to respective peripheral functions D A output enabled NOTE 1 1 Output Direction register Data bus Port latch Analog input Pull up selection NOT...

Page 271: ...fC Rf Rd Data bus Direction register Pull up selection Port latch 1 Output Direction register Pull up selection Port latch Data bus NOTE 1 NOTE 1 P8_7 P8_6 NOTE 1 Symbolizes a parasitic diode Make su...

Page 272: ...ALE RDY HOLD HLDA and BCLK cannot be modified Not available memory expansion and microprocessor modes in T V ver 3 When using the ports P11 to P13 set the PU37 bit in the PUR3 register to 1 usable 4 T...

Page 273: ...t port 1 Output mode Functions as an output port Nothing is assigned When write set to 0 When read their contents are indeterminate b7 b6 Nothing is assigned When write set to 0 When read their conten...

Page 274: ...00 bits are 01b memory expansion mode or 11b microprocessor mode Not available memory expansion and microprocessor modes in T V ver 2 During memory expansion and microprocessor modes the pins are not...

Page 275: ...PU37 P11_0 to P11_3 Pull Up P11_4 to P11_7 Pull Up P12_0 to P12_3 Pull Up P12_4 to P12_7 Pull Up P13_0 to P13_3 Pull Up P13_4 to P13_7 Pull Up P14_0 P14_1 Pull Up P11 to P14 Enabling Bit 0 Not pulled...

Page 276: ...4_5 CS1 to P4_7 CS3 ________ __________ BHE ALE HLDA XOUT 5 BCLK 6 ___________ ________ _______ HOLD RDY NMI P8_5 AVCC AVSS VREF After setting for input mode connect every pin to VSS via a resistor pu...

Page 277: ...n the 128 pin version When not using all of the P11 to p14 pins may be left open by setting the PU37 bit in the PUR3 register to 0 P11 to P14 unusable without causing any problem 3 Not available in T...

Page 278: ...e a 4K byte block A is programmed in 2 048 operations by writing one word at a time and erased thereafter In this case the block is reckoned as having been programmed and erased once If a product is 1...

Page 279: ...reset occurs while an H signal is applied to the CNVSS and P5_0 pins and an L signal is applied to the P5_5 pin refer to 21 1 1 Boot Mode A program in the user ROM area is executed after a hardware re...

Page 280: ...e to prevent the flash memory from reading or rewriting 21 2 1 ROM Code Protect Function The ROM code protect function inhibits the flash memory from being read or rewritten during parallel I O mode F...

Page 281: ...t reading or rewriting in parallel I O mode 3 Set the bit 5 to bit 0 to 111111b when the ROMCP1 bit is set to a value other than 11b If the bit 5 to bit 0 are set to values other than 111111b the ROM...

Page 282: ...ster mode Read array mode Erasing CPU Status during Auto Operating Maintains hold state I O ports maintains Write and Auto Erase the state before the command was executed 1 Flash Memory Status Read th...

Page 283: ...0 The software commands control programming and erasing The FMR0 register or the status register indicates whether a program or erase operation is completed as expected or not 21 3 2 EW1 Mode EW1 mode...

Page 284: ...he NMI pin is in the high state Also while in EW0 mode write to this bit from a program in other than the flash memory To set this bit to 0 in a read array mode 3 To set this bit to 1 write 0 and then...

Page 285: ...lash memory is disabled when the FMSTP bit is set to 1 Set the FMSTP bit by program in a space other than the flash memory Set the FMSTP bit to 1 if one of the followings occurs A flash memory access...

Page 286: ...o 21 3 8 Full Status Check 21 3 3 8 FMR11 Bit EW0 mode is entered by setting the FMR11 bit to 0 EW0 mode EW1 mode is entered by setting the FMR11 bit to 1 EW1 mode 21 3 3 9 FMR16 Bit This is a read on...

Page 287: ...area can be accessed 5 When in CPU rewrite mode the PM10 and PM13 bits in the PM1 register are set to 1 The rewrite control program can only be executed in the internal RAM or in an external area that...

Page 288: ...il oscillation clock source of oscillation stabilizes the CPU clock 2 Set the FMSTP bit to 0 flash memory operation Set the FMR01 bit to 0 CPU rewrite mode disabled Wait until the flash memory circuit...

Page 289: ...data in the flash memory 21 3 4 4 Interrupts EW1 Mode Do not acknowledge any interrupts with vectors in the relocatable vector table or address match interrupt during the auto program or auto erase pe...

Page 290: ...in the FMR0 register to 0 CPU rewrite mode disabled before executing the WAIT instruction 21 3 4 11 Stop Mode When the microcomputer enters stop mode execute the instruction which sets the CM10 bit t...

Page 291: ...bit write data BA Highest order block address must be an even address Any even address in the user ROM area xx High order 8 bits of command code ignored NOTE 1 It is only blocks 0 to 12 that can be e...

Page 292: ...n completed as expected Refer to 21 3 8 Full Status Check An address that is already written cannot be altered or rewritten Figure 21 8 shows a flow chart of the program command programming The lock b...

Page 293: ...ck from being programmed inadvertently Refer to 21 3 6 Data Protect Function In EW1 mode do not execute this command on the block where the rewrite control program is allocated In EW0 mode the microco...

Page 294: ...t the same time an auto erase operation starts It is set to 1 ready when an auto erase operation is completed The microcomputer remains in read status register mode until the read array command or rea...

Page 295: ...ghest order even address of a block in the second bus cycle the FMR16 bit in the FMR1 register stores information on whether or not the lock bit of a specified block is locked Read the FMR16 bit after...

Page 296: ...k bit status is retained If the block erase or erase all unlocked block command is executed while the FMR02 bit is set to 1 the target block or all blocks are erased regardless of lock bit status The...

Page 297: ...Sequencer status Terminated normally Terminated normally Busy Terminated in error Terminated in error Ready 0 Status Name Contents Bits in Status Register 1 FMR06 FMR07 FMR00 Bits in FMR0 Register Va...

Page 298: ...n locked blocks 2 The program command is executed on unlocked blocks but program operation is not completed as expected The lock bit program command is executed but program operation is not completed...

Page 299: ...te 1 2 and 3 at least 3 times until an erase error is not generated NOTE If similar error occurs that block cannot be used If the lock bit is set to 1 unlocked in 2 above that block cannot be used Whe...

Page 300: ...rea in the microcomputer mounted on a board For more information about the serial programmer contact your serial programmer manufacturer Refer to the user s manual included with your serial programmer...

Page 301: ...nal or open Input L level signal Input H or L level signal or open Standard serial I O mode 1 BUSY signal output pin Standard serial I O mode 2 Monitors the boot program operation check signal output...

Page 302: ...TXD SCLK EPM CE RXD BUSY M16C 6N Group M16C 6NK Flash memory version Connect oscillator circuit CNVSS EPM RESET CE Signal Mode setup method Value VCC1 VSS VSS to VCC1 VCC2 Package PLQP0100KB A 1 2 3...

Page 303: ...74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 8 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 31 32 33 34 35 36 37 66 67 68 69...

Page 304: ...external circuitry will vary according to programmer For more information refer to the programmer manual 2 In this example modes are switched between single chip mode and standard serial I O mode by...

Page 305: ...er for instructions 21 5 1 User ROM and Boot ROM Areas An erase block operation in the boot ROM area is applied to only one 4 Kbyte block The rewrite control program in standard serial I O and CAN I O...

Page 306: ...vel signal or open Input H or L level signal or open Input H or L level signal or open Input H level signal Input H or L level signal or open Input L level signal Input H or L level signal or open Inp...

Page 307: ...EPM CE M16C 6N Group M16C 6NK Flash memory version Connect oscillator circuit CNVSS EPM RESET CE SCLK TXD Signal Mode setup method Value VCC1 VSS VSS to VCC1 VCC2 VSS VCC1 Package PLQP0100KB A TXD 1 2...

Page 308: ...83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57...

Page 309: ...s manual of your CAN programmer to handle pins controlled by a CAN programmer CNVSS Microcomputer CAN_L CAN_H CAN_L CAN_H CAN transceiver P6_7 TXD1 P9_6 CTX0 P9_5 CRX0 P6_5 CLK1 RESET P8_5 NMI P5_0 C...

Page 310: ...hen the Microcomputer is Operating Temperature Flash Program Erase Storage Temperature Symbol Parameter _____________ RESET CNVSS BYTE P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7...

Page 311: ...to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P...

Page 312: ...3V 32 768 1 MHz kHz MHz MHz MHz ms kHz V V ms 0 16 0 16 50 24 24 20 10 0 5 0 3 0 3 0 3 f XIN f XCIN f Ring f PLL f BCLK tsu PLL f ripple VP P ripple VCC V T Parameter Symbol Typ Min Standard Unit Max...

Page 313: ...OUT HIGHPOWER LOWPOWER P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 t...

Page 314: ...n mode ROM 2 Flash Memory f BCLK 32kHz Low power dissipation mode RAM 2 f BCLK 32kHz Low power dissipation mode Flash memory 2 Mask ROM On chip oscillation Flash Memory Wait mode f BCLK 32kHz Wait mod...

Page 315: ...8 bits Differential Nonlinearity Error Offset Error Gain Error Resistor Ladder 10 bit Conversion Time Sample Hold Available 8 bit Conversion time Sample Hold Available Sampling Time Reference Voltage...

Page 316: ...C 3 0 to 5 5V Table 22 8 Flash Memory Version Electrical Characteristics 1 NOTES 1 Referenced to VCC 4 5 to 5 5V 3 0 to 3 6V Topr 0 to 60 C unless otherwise specified 2 Program and Erase Endurance ref...

Page 317: ...3 ns ns ns ns ns ns ns ns ns Data input access time for setting with no wait Data input access time for setting with wait Data input access time when accessing multiplexed bus area Data input setup t...

Page 318: ...nt decrement Input in Event Counter Mode ns ns ns TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Symbol Parameter Min Standard Unit Max 400 200 200 tc TA tw TAH tw TAL...

Page 319: ...ulse Width Measurement Mode Table 22 22 A D Trigger Input Table 22 23 Serial Interface ns ns ns TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Symbol Parameter Min Sta...

Page 320: ...rs to WR Data output hold time refers to WR 3 __________ HLDA output delay time Symbol Parameter Min Standard Unit Max 4 0 NOTE 1 4 4 0 0 4 NOTE 2 NOTE 1 Switching Characteristics Referenced to VCC 5V...

Page 321: ...output delay time refers to WR Data output hold time refers to WR 3 __________ HLDA output delay time Symbol Parameter Min Standard Unit Max 4 0 NOTE 1 4 4 0 0 4 NOTE 2 NOTE 1 Switching Characteristic...

Page 322: ...tput hold time Data output delay time refers to BCLK Data output hold time refers to BCLK Data output delay time refers to WR Data output hold time refers to WR __________ HLDA output delay time ALE s...

Page 323: ...td C Q th C D th C Q INTi input tc TB tw TBH tw TBL tc AD tw ADL ADTRG input TBiIN input Two phase pulse input in event counter mode tsu TAOUT TAIN tsu TAOUT TAIN tsu TAIN TAOUT tC TA tsu TAIN TAOUT...

Page 324: ...th VOL 2 5 V VOH 2 5 V BCLK HOLD input HLDA output P0 P1 P2 P3 P4 P5_0 to P5_2 1 NOTE 1 The above pins are set to high impedance regardless of the input level of the BYTE pin the PM06 bit in the PM0 r...

Page 325: ...td BCLK AD td BCLK ALE th BCLK ALE tSU DB RD td BCLK RD 40ns min tac1 RD DB Memory Expansion Mode and Microprocessor Mode For setting with no wait WR WRL WRH 25ns max th BCLK WR 0ns min BCLK CSi td B...

Page 326: ...BHE Read timing WR WRL WRH 25ns max th BCLK WR 0ns min BCLK CSi td BCLK CS 25ns max ADi td BCLK AD 25ns max ALE 25ns max td BCLK ALE th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th...

Page 327: ...td BCLK AD 25ns max td BCLK ALE 25ns max th BCLK ALE 4ns min td BCLK RD 25ns max Hi Z tSU DB RD 40ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc...

Page 328: ...td BCLK AD 25ns max td BCLK ALE 25ns max th BCLK ALE 4ns min td BCLK RD 25ns max Hi Z tSU DB RD 40ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc...

Page 329: ...WR 25ns max th BCLK WR 0ns min BCLK CSi td BCLK CS 25ns max ADi td BCLK AD 25ns max ALE 25ns max th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR AD BHE td BCLK DB 40ns max 4ns min...

Page 330: ...in tSU DB RD 40ns min th RD DB 0ns min th RD AD 0 5 tcyc 10 ns min th BCLK AD 4ns min td BCLK CS 25ns max td BCLK AD 25ns max th BCLK DB 4ns min th BCLK WR 0ns min th WR AD 0 5 tcyc 10 ns min th BCLK...

Page 331: ...P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0toP11_7 P12_0toP12_7 P13_0toP13_7 P14_0 P14_1 XOUT H...

Page 332: ...3 ns ns ns ns ns ns ns ns ns Data input access time for setting with no wait Data input access time for setting with wait Data input access time when accessing multiplexed bus area Data input setup t...

Page 333: ...ment decrement Input in Event Counter Mode ns ns ns TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Input LOW Pulse Width Symbol Parameter Min Standard Unit Max 600 300 300 tc TA tw TAH tw T...

Page 334: ...ulse Width Measurement Mode Table 22 40 A D Trigger Input Table 22 41 Serial Interface ns ns ns TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Symbol Parameter Min Sta...

Page 335: ...to WR Data output hold time refers to WR 3 __________ HLDA output delay time Symbol Parameter Min Standard Unit Max 4 0 NOTE 1 4 4 0 0 4 NOTE 2 NOTE 1 Switching Characteristics Referenced to VCC 3 3V...

Page 336: ...tput delay time refers to WR Data output hold time refers to WR 3 __________ HLDA output delay time Symbol Parameter Min Standard Unit Max 4 0 NOTE 1 4 4 0 0 4 NOTE 2 NOTE 1 Switching Characteristics...

Page 337: ...ut hold time Data output delay time refers to BCLK Data output hold time refers to BCLK Data output delay time refers to WR Data output hold time refers to WR __________ HLDA output delay time ALE sig...

Page 338: ...td C Q th C D th C Q INTi input tc TB tw TBH tw TBL tc AD tw ADL ADTRG input TBiIN input Two phase pulse input in event counter mode tsu TAOUT TAIN tsu TAOUT TAIN tsu TAIN TAOUT tC TA tsu TAIN TAOUT...

Page 339: ...h VOL 1 65 V VOH 1 65 V BCLK HOLD input HLDA output P0 P1 P2 P3 P4 P5_0 to P5_2 1 NOTE 1 The above pins are set to high impedance regardless of the input level of the BYTE pin the PM06 bit in the PM0...

Page 340: ...d BCLK AD td BCLK ALE th BCLK ALE tSU DB RD td BCLK RD 50ns min tac1 RD DB Memory Expansion Mode and Microprocessor Mode For setting with no wait WR WRL WRH 30ns max th BCLK WR 0ns min BCLK CSi td BCL...

Page 341: ...E Read timing WR WRL WRH 30ns max th BCLK WR 0ns min BCLK CSi td BCLK CS 30ns max ADi td BCLK AD 30ns max ALE 30ns max td BCLK ALE th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR...

Page 342: ...BCLK AD 30ns max td BCLK ALE 30ns max th BCLK ALE 4ns min td BCLK RD 30ns max Hi Z tSU DB RD 50ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc Hi...

Page 343: ...BCLK AD 30ns max td BCLK ALE 30ns max th BCLK ALE 4ns min td BCLK RD 30ns max Hi Z tSU DB RD 50ns min th RD DB 0ns min th BCLK RD 0ns min th RD AD 0ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc Hi...

Page 344: ...ns max th BCLK WR 0ns min BCLK CSi td BCLK CS 40ns max ADi td BCLK AD 40ns max ALE 40ns max th BCLK ALE 4ns min th BCLK AD 4ns min th BCLK CS 4ns min tcyc th WR AD BHE td BCLK DB 50ns max 4ns min th B...

Page 345: ...tSU DB RD 50ns min th RD DB 0ns min th RD AD 0 5 tcyc 10 ns min th BCLK AD 4ns min td BCLK CS 40ns max td BCLK AD 40ns max th BCLK DB 4ns min th BCLK WR 0ns min th WR AD 0 5 tcyc 10 ns min th BCLK AD...

Page 346: ...puter is Operating Temperature Flash Program Erase Storage Temperature Symbol Parameter _____________ RESET CNVSS BYTE P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_...

Page 347: ...to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 P7_2 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 P9_2 to P9_7 P10_0 to P10_7 P11_0 to P11_7 P12_0 to P12_7 P13_0 to P13_7 P14_0 P14_1 P0_0 to P0_7 P1_0 to...

Page 348: ...ient VCC 5V 32 768 1 MHz kHz MHz MHz MHz ms kHz V V ms 0 16 0 16 50 20 20 20 10 0 5 0 3 f XIN f XCIN f Ring f PLL f BCLK tsu PLL f ripple VP P ripple VCC V T Parameter Symbol Typ Min Standard Unit Max...

Page 349: ...POWER LOWPOWER XCOUT HIGHPOWER LOWPOWER P0_0 to P0_7 P1_0 to P1_7 P2_0 to P2_7 P3_0 to P3_7 P4_0 to P4_7 P5_0 to P5_7 P6_0 to P6_7 P7_0 to P7_7 P8_0 to P8_4 P8_6 P8_7 P9_0 to P9_7 P10_0 to P10_7 P11_0...

Page 350: ...n mode RAM 2 f BCLK 32kHz Low power dissipation mode Flash memory 2 Mask ROM On chip oscillation Flash Memory Wait mode f BCLK 32kHz Wait mode 3 Oscillation capacity High f BCLK 32kHz Wait mode 3 Osci...

Page 351: ...2 This applies when using one D A converter with the DAi register i 0 1 for the unused D A converter set to 00h The resistor ladder of the A D converter is not included Also the current IVREF always f...

Page 352: ...Voltage VCC 4 2 to 5 5V NOTES 1 Referenced to VCC 4 5 to 5 5V Topr 0 to 60 C unless otherwise specified 2 Program and Erase Endurance refers to the number of times a block erase can be performed If t...

Page 353: ...al Trigger Input in Pulse Width Modulation Mode Table 22 61 Timer A Input Counter Increment decrement Input in Event Counter Mode ns ns ns TAiIN Input Cycle Time TAiIN Input HIGH Pulse Width TAiIN Inp...

Page 354: ...se Width Measurement Mode Table 22 66 A D Trigger Input Table 22 67 Serial Interface ns ns ns TBiIN Input Cycle Time TBiIN Input HIGH Pulse Width TBiIN Input LOW Pulse Width Symbol Parameter Min Stand...

Page 355: ...d C Q th C D th C Q INTi input tc TB tw TBH tw TBL tc AD tw ADL ADTRG input TBiIN input Two phase pulse input in event counter mode tsu TAOUT TAIN tsu TAOUT TAIN tsu TAIN TAOUT tC TA tsu TAIN TAOUT TA...

Page 356: ...Set Counter ICTB2 01CDh SI O6 Bit Rate Generator 2 S6BRG 01D9h SI O3 Bit Rate Generator S3BRG 01E3h SI O4 Bit Rate Generator S4BRG 01E7h SI O5 Bit Rate Generator 2 S5BRG 01EBh UART2 Bit Rate Generato...

Page 357: ...C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution Under development This document is under development and its contents are subject to change 23 2 External Bus Normal ver only When resetting CNVSS pin...

Page 358: ...M16C 6NK M16C 6NM 23 Usage Precaution Under development This document is under development and its contents are subject to change 23 3 External Clock Do not stop the external clock when it is connect...

Page 359: ...NK M16C 6NM 23 Usage Precaution Under development This document is under development and its contents are subject to change 23 4 PLL Frequency Synthesizer Stabilize supply voltage so that the standard...

Page 360: ...queue roadstead the instructions following WAIT and depending on timing some of these may execute before the microcomputer enters wait mode Program example when entering wait mode Program Example JMP...

Page 361: ...rts that high impedance state When entering wait mode or stop mode set non used ports to input and stabilize the potential A D converter When A D conversion is not performed set the VCUT bit in the AD...

Page 362: ...t oscillation stop re oscillation stop detection Figure 23 1 Operation Timing at Oscillation Stop Re oscillation Stop Detection at Wait Mode ________ when moving out of wait mode by using INT0 interru...

Page 363: ...change 23 7 Protection Set the PRC2 bit to 1 write enabled and then write to any address and the PRC2 bit will be set to 0 write protected The registers protected by the PRC2 bit should be changed in...

Page 364: ...go out of control _______ Especially when using NMI interrupt set a value in the ISP at the beginning of the program For the first _______ and only the first instruction after reset all interrupts in...

Page 365: ...bits in the IFSR1 register or the IFSR23 to IFSR25 bits 3 in the IFSR2 register are changed the IR bit may inadvertently set to 1 interrupt requested Be sure to set the IR bit to 0 interrupt not requ...

Page 366: ...ion to set the IR bit to 0 c When using the I flag to disable an interrupt refer to the sample program fragments shown below as you set the I flag Refer to b for details about rewrite the interrupt co...

Page 367: ...The DMAS bit remains unchanged even if 1 is written However if 0 is written to this bit it is set to 0 DMA not requested In order to prevent the DMAS bit from being modified to 0 1 should be written...

Page 368: ...re the TAiMR register is modified while the TAiS bit remains 0 count stops regardless whether after reset or not While counting is in progress the counter value can be read out at any time by reading...

Page 369: ...in the ONSF register and the TRGSR register are modified while the TAiS bit remains 0 count stops regardless whether after reset or not While counting is in progress the counter value can be read out...

Page 370: ...xternal trigger has been selected one cycle delay of a count source as maximum occurs between a trigger input to TAiIN pin and output in one shot timer mode The IR bit is set to 1 when timer operation...

Page 371: ...The IR bit is set to 1 when setting a timer operation mode with any of the following procedures Select the pulse width modulation mode after reset Change an operation mode from timer mode to pulse wid...

Page 372: ...ter while counting can be read in the TBi register at any time FFFFh is read while reloading Setting value is read between setting values in the TBi register at count stop and starting a counter 23 10...

Page 373: ...upt request can be determined by use of the MR3 bit in the TBiMR register within the interrupt routine If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse...

Page 374: ...t you may write data to TAi 1 register i 1 2 4 near Timer B2 overflow read the value of TB2 register verify that there is sufficient time until Timer B2 overflows before doing an immediate write to TA...

Page 375: ...t in UiTB register _______ ________ If CTS function is selected input on the CTSi pin L 23 12 1 3 Reception In operating the clock synchronous serial I O operating a transmitter generates a shift cloc...

Page 376: ...condition generate bit STAREQ RSTAREQ and STPREQ bits from 0 clear to 1 start 23 12 2 2 Special Mode 2 _______ If a low level signal is applied to the NMI pin when the IVPCR1 bit in the TB2SC registe...

Page 377: ...egister bit approximately 10ns may be output when changing the SMi3 bit in the SiC register from 0 I O port to 1 SOUTi output and CLKi function while the SMi2 bit in the SiC register to 0 SOUTi output...

Page 378: ...e sure the port direction bits for those pins that are used as analog inputs are set to 0 input mode Also if the TGR bit in the ADCON0 register 1 external trigger make sure the port direction bit for...

Page 379: ...completed When operating in repeat mode or repeat sweep mode 0 or 1 Use the main clock for CPU clock directly without dividing it If A D conversion is forcibly terminated while in progress by setting...

Page 380: ...lowing points so that the access period from the CPU should not match the updating period of the CAN module a There should be a wait time of 3fCAN or longer see Table 23 3 CAN Module Status Updating P...

Page 381: ...reset mode for the CPU read has the higher priority Figure 23 6 With a Wait Time of 3fCAN Before CPU Read Figure 23 7 When Polling Period of CPU is 3fCAN or Longer Updated without fail in period of 3...

Page 382: ...sure to check that the State_Reset bit in the CiSTR register is set to 1 reset mode Similarly if the Reset bit is changed from 1 to 0 in order to place the CAN module from CAN reset initialization mo...

Page 383: ...an 170 A less than 70 mA CAN Transceiver 2 CAN Communication impossible possible Connection i 0 1 NOTES 1 The pin which controls the operation mode of CAN transceiver 2 In case of Ta 25 C 3 Connect to...

Page 384: ...case of PCA82C250 Philips product Standby Mode High speed Mode Rs Pin 1 H L CAN Communication impossible possible Connection i 0 1 NOTES 1 The pin which controls the operation mode of CAN transceiver...

Page 385: ...age of pins differs between programmable I O ports and peripheral functions Therefore if any pin is shared by a programmable I O port and a peripheral function and the input level at this pin is outsi...

Page 386: ...en different power supplied to the system and input voltage of unused dedicated input pin is larger than voltage of VCC pin connect dedicated input pin to VCC via resistor approximately 1k Figure 23 8...

Page 387: ...cteristic Differences Between Mask ROM and Flash Memory Version Microcomputers Flash memory version and mask ROM version may have different characteristics operating margin noise tolerated dose noise...

Page 388: ...124 0200 M16C 6N Group M16C 6NK M16C 6NM 23 Usage Precaution Under development This document is under development and its contents are subject to change 23 18 Mask ROM Version When using the masked RO...

Page 389: ...e WAIT instruction 23 19 4 LowPowerDissipationModeandOn ChipOscillatorLowPowerDissipationMode If the CM05 bit is set to 1 main clock stopped do not execute the following commands Program Block erase E...

Page 390: ...match interrupt during the auto program or auto erase period Do not use the watchdog timer interrupt _______ The NMI interrupt is available since the FMR0 and FMR1 registers are forcibly reset when t...

Page 391: ...serial I O mode Figure 23 9 Pin Connection for Programming Using Serial I O Mode 23 20 2 Programming Using CAN I O Mode _________ RTS1 pin This pin automatically outputs H and L level Figure 23 10 sho...

Page 392: ...Noise Connect a bypass capacitor approximately 0 1 F across the VCC1 and VSS pins and VCC2 and VSS pins using the shortest and thicker possible wiring Figure 23 11 shows the bypass capacitor connectio...

Page 393: ...Symbol Dimension in Millimeters Min Nom Max 0 15 0 20 0 25 0 09 0 145 0 20 0 08 1 0 1 0 0 18 0 125 1 0 Previous Code JEITA Package Code RENESAS Code PLQP0100KB A 100P6Q A FP 100U FP 100UV MASS Typ 0 6...

Page 394: ...00 Nov 28 2005 page 376 of 378 REJ09B0124 0200 M16C 6N Group M16C 6NK M16C 6NM Appendix 1 Package Dimensions Under development This document is under development and its contents are subject to change...

Page 395: ...ON 106 DM0IC DM1IC 86 DM0SL 105 DM1SL 106 DTT 142 F FMR0 266 FMR1 266 I ICTB2 144 IDB0 IDB1 142 IFSR0 95 IFSR1 96 IFSR2 97 INT0IC to INT8IC 87 INVC0 140 INVC1 141 K KUPIC 86 O ONSF 118 P P0 to P13 255...

Page 396: ...his document is under development and its contents are subject to change U U0BCNIC to U2BCNIC 86 U0BRG to U2BRG 153 U0C0 to U2C0 154 U0C1 to U2C1 155 U0MR to U2MR 154 U0RB to U2RB 153 U0SMR to U2SMR 1...

Page 397: ...Type No Memory Size and Package Characteristics is added 13 FIgure 4 1 SFR Information 1 The value of After Reset in CM2 Register is revised 19 Figure 4 7 SFR Information 7 NOTE 1 is revised 39 Figure...

Page 398: ...Electric Characteristics of T V ver is added Revised parts and revised contents are as follows except for expressional change 1 1 1 Applications Comment of T V ver is added 2 Table 1 1 Performance Ou...

Page 399: ...PLL Clock Frequencies NOTES 2 and 3 are added 68 8 2 1 CPU Clock and BCLK 10th line The sentence During memory expansion is added 69 8 4 1 2 PLL Operation Mode NOTE 1 is added 70 8 4 1 6 On chip Oscil...

Page 400: ...to 11b NOTE 1 is added 217 16 2 6 Output Impedance of Sensor under A D Conversion 10th line f XIN is revised to f AD 218 Figure 16 10 Analog Input Pin and External Sensor Equivalent Circuit fAD is re...

Page 401: ...emory expansion mode is added NOTE 5 is revised and NOTE6 is added Figure 21 6 Setting and Resetting of EW1 Mode NOTE 1 is revised 270 Figure 21 7 Processing Before and After Low Power Dissipation Mod...

Page 402: ...am 2 to 8 are added 313 to 327 Characteristics of 3 3 V in Normal ver are added 328 to 337 22 2 Electrical Characteristics T V ver is added 339 23 2 External Bus Normal ver only is added 342 23 5 Powe...

Page 403: ...6NK M16C 6NM Hardware Manual Publication Data Rev 1 00 Sep 30 2004 Rev 2 00 Nov 28 2005 Published by Sales Strategic Planning Div Renesas Technology Corp 2005 Renesas Technology Corp All rights reserv...

Page 404: ...M16C 6N Group M16C 6NK M16C 6NM Hardware Manual 2 6 2 Ote machi Chiyoda ku Tokyo 100 0004 Japan...

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Renesas M16C/6NK, Hardware Manual, Page: 307 / 404

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