Renesas IDT Tsi574, User Manual

Page: 225 / 514

225
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12. Serial RapidIO Registers
This chapter describes the Tsi574 registers. The following topics are discussed:
• “Overview” on page 225
• “Port Numbering” on page 227
• “Conventions” on page 227
• “Register Map” on page 228
• “RapidIO Logical Layer and Transport Layer Registers” on page 238
• “RapidIO Physical Layer Registers” on page 261
• “RapidIO Error Management Extension Registers” on page 277
• “IDT-Specific RapidIO Registers” on page 299
• “Serial Port Electrical Layer Registers” on page 353
• “Internal Switching Fabric (ISF) Registers” on page 372
• “Utility Unit Registers” on page 377
• “Multicast Registers” on page 383
• “SerDes Per Lane Register” on page 390
12.1 Overview
The application defined Tsi574 registers receive initial values during power on initialization through
the I
2
C Interface and external serial EEPROM; all undefined registers read 0 and a write is ignored.
The Tsi574 registers use direct addressing of 32-bit registers. The RapidIO Interconnect Specification
(Revision 1.3) , uses 64-bit addressing of registers. Table 32 shows the rules used to associate the
register offsets in both specifications.
Table 32: Address Rules
Tsi574 Address — Register Offset RapidIO Specification Address — Register Offset
0x XXXX 0 0x XXXX 0, Word 0
0x XXXX 4 0x XXXX 0, Word 1
0x XXXX 8 0x XXXX 8, Word 0
0x XXXX C 0x XXXX 8, Word 1