Renesas IDT Tsi574, User Manual

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12. Serial RapidIO Registers > Serial Port Electrical Layer Registers 353
Tsi574 User Manual
June 6, 2016
Integrated Device Technology
www.idt.com
12.10 Serial Port Electrical Layer Registers
The Serial Port Electrical Layer Registers are not defined in the RapidIO Interconnect Specification
(Revision 1.3) . They are specific to IDT’s switching products.
These registers are reset by the HARD_RST_b reset input signal, as well as when the Tsi574 performs
a self-reset. The registers within a port are also reset by a
“Port Reset” . For more information on Tsi574
reset implementation and behavior, see “Clocks, Resets and Power-up Options” on page 203 .
It is possible to override reset values of writable fields, and some read-only fields, using the I
2
C
register loading capability on boot. Refer to “I
2
C Interface” on page 139 for more information on the
use of I
2
C controller register loading capability.
The registers in the following table are accessible even when the serial RapidIO ports are in reset or
powered down.
Software must not access reserved addresses or bits, because this can affect device operation
in non-deterministic ways.
Table 44: IDT-Specific RapidIO Registers
Port Register Offset Description
BC 10000 Broadcast addresses. These
registers affect all the ports.
SP0 11000 1x/4x serial port
SP1 11100 1x serial port
SP2 11200 1x/4x serial port
SP3 11300 1x serial port
SP4 11400 1x/4x serial port
SP5 11500 1x serial port
SP6 11600 1x/4x serial port
SP7 11700 1x serial port
Table 45: Serial Port Electrical Layer Registers
MAC Register Offset Description
MAC0 130B0 Ports 0 and 1
MAC2 132B0 Ports 2 and 3