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1.1 General CPU Architecture
1.1.1 Features
Table 1-1 summarizes the CPU architecture. Figures 1-1 and 1-2 show how data are
stored in registers and memory.
Table 1-1. CPU Architecture
Notes:
1.
Word data stored in memory must be stored at an even address.
2.
Instructions must be stored at even addresses.
3.
General register R7 is used as the stack pointer (SP).
1.1.2 Data Structure
The H8/300 CPU can process 1-bit data, 4-bit (packed BCD) data, 8-bit (byte) data, and 16-bit
(word) data.
•
Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a
byte operand.
•
All operational instructions except ADDS and SUBS can operate on byte data.
Item
Description
Address space
64K bytes, H'0000 to H'FFFF
Data types
Bit, 4-bit (packed BCD), byte, word (2 bytes)
General registers
Sixteen 8-bit general registers (R0H, R0L, ..., R7H, R7L),
also accessible as eight 16-bit general registers (R0 to R7)
Control registers
Program counter (PC)
Condition code register (CCR)
Addressing modes
Rn
Register direct
@Rn
Register indirect
@(d:16, Rn)
Register indirect with 16-bit displacement
@Rn+
Register indirect with post-increment
@–Rn
Register indirect with pre-decrement
@aa:8, @aa:16
Absolute address (8 or 16 bits)
#xx:8, #xx:16
Immediate (8-, or 16-bit data)
@(d:8, PC)
PC-relative (8-bit displacement)
@@aa:8
Memory indirect
Instruction length
2 or 4 bytes
2
Summary of Contents for H8/300 Series
Page 2: ...H8 300 Programming Manual...