ForgeFPGA Configuration Guide
Rev.1.0
May 31, 2022
Page 11
Figure 12. OTP Read Timing
6.3 Read Command Structure
Table 5: NVM OTP Read Command Packet Format
Bits
0
1
2
3
4
5
6
7
Byte 1
nRead (0)
0
R
R
R
R
R
R
Byte 2
A[18]
A[17]
A[16]
A[15]
A[14]
A[13]
A[12]
A[11]
Byte 3
A[10]
A[4]
A[3]
A[2]
A[1]
A[0]
0
P
Byte 1 of the packet will remain the same across all read operations and contains only the read command bit
(Byte1[0]). Byte1 Bits[7:2] are reserved (R) bits. A read address is then provided across Bytes 2 and 3, before a
parity bit (P) is provided at the MSB of Byte 3. This read address is separated into two sections. A[18:17]
determines which of the three 4 k x32 NVM blocks to read from (named OTP1, OTP2, and OTP3) and A[16:10]
A[4:0] determines the address within the specified NVM block to read. The parity bit to be provided is calculated
by performing an AND operation of all incoming bytes, excluding the parity bit =
(^Byte1)^(^Byte2)^(^[Byte3[0:6]]).
Table 6: NVM Block Selection
NVM Block
Selection
Address to Read
A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10]
A[4]
A[3]
A[2]
A[1]
A[0]
7. QSPI Programming (Master Mode)
In SPI Master mode, the communication starts by driving SPI_SS Low, and then sends a Release from Power-
down command to SPI Flash, 0xAB. The timing diagram below provides an example waveform. This initial
command wakes up the SPI Flash if it is already in Deep Power-down Mode (see
). The SPI Master
transmits data on the SPI_SO output, on the falling edge of the SPI_CLK output. No data is sent on SPI_SI
currently. After sending the last command bit, the SPI_SS is de-asserted High, completing the command.
Minimum of 10 us buffer is given before sending the next SPI Flash command.
represents the pins in SLG47910 corresponding the pins in SPI
Table 7: SPI Pin Numbers
QFN Pin No
Pin Name
QSPI/SPI Mode
16
GPIO3
SPI_CLK
17
GPIO4
SPI_SS
