8V19N850 Hardware Design Guide
X0120307 Rev.1.0
Mar 25, 2021
Page 2
Figure 2. 8V19N850 Reference Schem atic Exam ple
1. Power Rails
1.1
Bypass Capacitors
To avoid signal interference, bypass capacitors are required to filter noise from switching power supplies and
other devices in the system. Figure 2 shows examples of bypass capacitors on the schematic. The type of
bypass capacitor will depend on the noise level and noise frequencies on the application board. The device
output driver switching can also cause power rail noise and interference with noise signals from other devices on
the board, resulting in unwanted spurious tones in output signals. The bypass capacitors minimize these noise
sources.
The bypass capacitor values are usually in the range from 0.01µF to 0.1µF. Other values can also be used.
Typical capacitor sizes are 0603, 0402, or 0201 with a low Equivalent Series Resistance (ESR). The dielectric
types are typically X5R or X7R. A smaller size allows the capacitor to be placed closer to the power pin of the
device with a reduced trace length.
LVDS Style Termination Ex ample
C
22
0
.1
uF
Zo = 50
Q
C
LK
_
D
1
3
VDDO_R4
C6
1.0uF
C95
100pF
R7
R9
5.1k
R28
1
VDD_OSC
nQREF_R0
3
nQREF_R1
3
R24
100
C1
C70
0.1uF
C56
100pF
C43
0.1uF
n
C
L
K
1
2
C
48
1
00
p
F
C59
10uF
C53
10uF
QREF_R5
3
Zo
C
34
1
0u
F
C49
10uF
C41
100pF
R20
1
VDDO_R23
VDDO_Dx
R27
1k
1
k
R30
1
Keep close to DUT
Loop Filter - Keep close to DUT
C5
0
.1
uF
L18
220
C
84
0
.1
uF
R1
100
QCLK_R0
R2
C
30
1
0u
F
L17
220
C
47
0
.1
uF
C
80
0
.1
uF
SD
O_SD
A
5
C23
10uF
R26
1k
1
k
Keep close to DUT
L8
220
C38
0.1uF
C9
0
.1
uF
C72
10uF
C96
0.1uF
QREF_R3
3
C15
0.1uF
L5
220
C
20
0
.1
uF
C50
100pF
QCLK_R2
C
13
1
0u
F
VDD_INP
GPIO_2
3
VDDO_REF
n
Q
C
L
K
_D
2
3
VDD_APLL
Ro
PD
C55
0.1uF
Q
C
LK
_
D
0
3
VDD_DPLL0
C74
0.1uF
C10
22uF
R13
510
C
93
0
.1
uF
n
Q
C
L
K
_D
0
3
SPI
_
SEL
2
R18
1
L9
220
C42
0.1uF
C
37
1
00
pF
R6
5.1K
SD
I
5
QREF_R1
3
SC
LK_
SC
L
5
C18
10uF
L7
220
C
68
0
.1
uF
VDD_XO
C
LK
1
2
C
82
1
00
p
F
U1
8V19N850
VDD_DPLL0
1
VDDO_REF_2
2
QREF_R0
3
nQREF_R0
4
QREF_R1
5
nQREF_R1
6
QREF_R2
7
nQREF_R2
8
QREF_R3
9
nQREF_R3
10
QREF_R4
11
nQREF_R4
12
QREF_R5
13
nQREF_R5
14
VDDO_REF_15
15
CAP_APLL
16
VDD_APLL
17
CP_APLL
18
GPIO_0
19
GPIO_1
20
GPIO_2
21
GPIO_3
22
VD
D
_GPI
O
2
3
Q
C
LK
_
D
0
2
4
SPI
_
SEL
3
6
V
DDO
_
D3
3
5
n
Q
C
L
K
_D
3
3
4
Q
C
LK
_
D
3
3
3
V
DDO
_
D2
3
2
n
Q
C
L
K
_D
2
3
1
Q
C
LK
_
D
2
3
0
V
DDO
_
D1
2
9
n
Q
C
L
K
_D
1
2
8
Q
C
LK
_
D
1
2
7
V
DDO
_
D0
2
6
n
Q
C
L
K
_D
0
2
5
nQCLK_R4
48
VDDO_R4_47
47
DNU-46
46
DNU_45
45
V
DD_
RFV
CO
4
4
C
AP_R
F
PL
L
4
3
CP
_
RFP
L
L
4
2
V
DD_
RFP
L
L
4
1
V
D
D
O
_
R
5_
4
0
4
0
n
Q
C
L
K
_R
5
3
9
Q
C
LK
_
R
5
3
8
V
DDO
_
R5
3
7
QCLK_R4
49
VDDO_R4_50
50
VDDO_R23_51
51
nQCLK_R3
52
QCLK_R3
53
nQCLK_R2
54
QCLK_R2
55
VDDO_R23_56
56
VDDO_R01_57
57
nQCLK_R1
58
QCLK_R1
59
nQCLK_R0
60
QCLK_R0
61
VDDO_R01_62
62
VDD_DPLL1
63
CP_DPLL1
64
CAP_DPLL1
65
VDD_DC01
66
V
DD_
INP
6
7
n
C
L
K
1
6
8
C
LK
1
6
9
n
C
L
K
0
7
0
C
LK
0
7
1
VD
D
_SPI
7
2
n
CS
/A
DR0
7
3
SC
LK/
SC
L
7
4
SD
O/
SD
A
7
5
S
DI
/A
DR1
7
6
EXT
_SYS
7
7
S
C
L_
M
7
8
SD
A_M
7
9
OSC
O
8
0
OSC
I
8
1
VR
EG_
OSC
_
C
AP
8
2
VD
D
_OSC
8
3
n
X
O
_
D
P
L
L
8
4
XO_D
PLL
8
5
VD
D
_XO
8
6
C
P
_D
P
LL
0
8
7
C
A
P
_
D
P
L
L
0
8
8
EP
8
9
L1
220
C3
0
.1
uF
VDD_GPIO
L6
220
C
46
0
.1
uF
C69
33pF
VDD_RFPLL
C
61
1
0u
F
R17
1
L2
220
C65
10uF
C7
0
.1
uF
C77
10uF
Q
C
LK
_
R
5
3
C88
0.1uF
L21
220
C97
0.1uF
nQREF_R4
3
nQCLK_R3
R21
300
VDDO_Dx
R8
100
C63
22uF
VCC=3.3V
L20
220
C
92
0
.1
uF
GPIO_0
3
C25
0.1uF
Q
C
LK
_
D
2
3
C
86
1
00
p
F
C58
0.1uF
GPIO_1
3
C52
0.1uF
CLK
nCLK
nQREF_R2
3
R32
1
nQCLK_R1
C
36
0
.1
uF
L14
220
C
66
0
.1
uF
VDD_DPLL1
n
C
S
5
nQCLK_R0
C32
10uF
Keep close to DUT
VDDO_Dx
C
83
1
0u
F
Ro
C
31
0
.1
uF
C
79
1
0u
F
L13
220
SD
A_M
5
R10 1
PD
C27
22uF
OCXO/TCXO LVCMOS
L12
220
C39
10uF
C71
0.1uF
L19
220
C89
0.1uF
C87
100pF
C
21
1
0u
F
Zo = 50
C
14
0
.1
uF
R23 1
VDDO_Dx
C26
33pF
C54
33pF
QREF_R4
3
EXT
_SYS
2
VCC=3.3V
VDD
C24
470pF
QCLK_R3
R33
1
n
Q
C
L
K
_D
3
3
R29
1
QREF_R0
3
Keep close to DUT
C44
10uF
C57
0.1uF
L11
220
C51
0.1uF
VDDO_REF
C19
0.1uF
C
35
0
.1
uF
R19
1
JP2
GPIO_1
Loop Filter - Keep close to DUT
C4
1
0u
F
QREF_R2
3
XO/OCXO/TCXO LVCMOS
QCLK_R1
R5
100
C33
0.1uF
C
29
0
.1
uF
C
94
1
00
p
F
n
Q
C
L
K
_D
1
3
C
45
1
0u
F
C
62
0
.1
uF
JP1
GPIO_0
R14 1
C8
1
0u
F
C76
0.1uF
L16
220
C73
0.1uF
C98
10uF
C16
22uF
LVDS Driv er
L3
220
C
12
0
.1
uF
R31
1
n
Q
C
L
K
_R
5
3
S
C
L_
M
5
VDDO_R01
VDDO_R5
C64
0.1uF
R16
2k
C75
22uF
C11
0.1uF
nQREF_R5
3
R12
NP
R3
100
C
91
1
0u
F
VDD_DCO1
Update pin name
R4
100
PU
Zo = 50
Zo = 50
L4
220
C17
0.1uF
C
67
1
0u
F
VDD_SPI
Q
C
LK
_
D
3
3
PU
C2
Loop Filter - Keep
close to DUT
GPIO_3
3
nQREF_R3
3
C
85
0
.1
uF
nQCLK_R2
L10
220
R22
1
R25
200
C
81
0
.1
uF
C
60
0
.1
uF
VDD_RFVCO
C28
0.1uF
VDD_XO
Zo
L15
220
C40
0.1uF
C78
0.1uF
C90
10uF
R11
1
