Renesas 89HPES24T3G2ZBAL, User Manual

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Notes
PES24T3G2 User Manual 2 - 1 February 22, 2012
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Chapter 2
Clocking, Reset and
Initialization
Clocking
The PES24T3G2 has a single differential reference clock input (PEREFCLKP/PEREFCLKN) that is
used internally to generate all of the clocks required by the internal switch logic and the SerDes. The
frequency of the reference clock input is set to 100MHz.
Note: There are no skew requirement between the reference clock inputs.
Initialization
A boot configuration vector consisting of the signals listed in Table 2.1 is sampled by the PES24T3G2
during a Fundamental Reset when PERSTN is negated. The boot configuration vector defines essential
parameters for switch operation. Since the boot configuration vector is sampled only during a Fundamental
Reset sequence, the value of signals which make up the boot configuration vector is ignored during other
times and their state outside of a Fundamental Reset has no effect on the operation of the PES24T3G2.
While basic switch operation may be configured using signals in the boot configuration vector, advanced
switch features require configuration via an external serial EEPROM. The external serial EEPROM allows
modification of any bit in any software visible register. See Chapter 5, SMBus Interfaces, for more informa-
tion on the serial EEPROM.
The external serial EEPROM and slave SMBus interface may be used to override the function of some
of the signals in the boot configuration vector during a Fundamental Reset. The signals that may be over-
ridden are noted in Table 2.1. The state of all of the boot configuration signals in Table 2.1 sampled during
the most recent Fundamental Reset may be determined by reading the SWSTS register.
Signal
May Be
Overridden
Description
CCLKDS I Common Clock Downstream. The assertion of this pin indicates
that all downstream ports are using the same clock source as that
provided to downstream devices.This bit is used as the initial value
of the Slot Clock Configuration bit in all of the Link Status Registers
for downstream ports. The value may be overridden by modifying
the SCLK bit in each downstream port’s PCIELSTS register.
CCLKUS I Common Clock Upstream. The assertion of this pin indicates that
the upstream port is using the same clock source as the upstream
device. This bit is used as the initial value of the Slot Clock Configu-
ration bit in the Link Status Register for the upstream port. The value
may be overridden by modifying the SCLK bit in the P0_PCIELSTS
register.
MSMBSMODE
1
I Master SMBus Slow Mode. The assertion of this pin indicates that
the master SMBus should operate at 100 KHz instead of 400 KHz.
This value may not be overridden.
Table 2.1 Boot Configuration Vector Signals