3Ć3
Read register 4 to determine whether bits 8 and 10 are set,
signifying that the common clock is being driven by
another module in the rack. If they are not set, then set
registers 5 and 6 on this module to the value 64. This will
enable common clock on this module. Bits 8 and 10 on
register 4 should now be set.
Monitor registers 0 and 1. Verify that they contain numbers
proportional to the analog value on their respective
channels. This confirms that the installation is complete.
Refer to table 1 for the approximate voltages or currents
that should be read.
Table 1
+
+
ă4095
+1.0V
+10.0V
20 ma
ăă819
+ă.2V
+2.0V
ă4 ma
ăăă0
0.0V
0.0V
ă0 ma
-4095
-1.0V
-10.0V
ă -
Step 9.
Determine offset and gain compensation. This is
necessary because manufacturing tolerances on the
module can result in small offset and gain differences (See
figure 3.3).
VOLTS
0
4095
10
COUNTS
CORRECTED_VALUE%
OFFSET
RAW_DATA%
Figure 3.3 Ć Offset and Gain
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