M
M
o
o
d
d
u
u
l
l
e
e
I
I
n
n
t
t
e
e
g
g
r
r
a
a
t
t
i
i
o
o
n
n
G
G
u
u
i
i
d
d
e
e
V
V
e
e
r
r
s
s
i
i
o
o
n
n
2
2
.
.
1
1
Redpine Signals, Inc. Proprietary and Confidential
Page 43
2.2.4
SPI mode Interface Schematic
MCU pin
driving
RESET_N
H os t M C U may direc tly drive the RE SE T _N
pin of the module as s hown below.
OPTION-3
RS9113 based
Module
HOST MCU
RESET_N
R13
10K
Note: Ensure a reset assertion time of 20ms.
FB10
BEAD
ANA3V3
C26
1uF
FB11
BEAD
Power Supply Filter Section
VDD_EXT
C11
0.1uF
FB8
BEAD
VIN_33
VRF33
DVDD33
C9
0.1uF
FB6
BEAD
C8
47uF(CASE B)
FB7
BEAD
C17
2.2uF
C18
22uF(CASE B)
Tantalum
C24
0.1uF
C19
0.1uF
R14
4.7K
VINMOD
C25
1uF
L1
4.7uH
R16
100K
Note:
R23 should be mounted for USB Enumeration
R23 should not be mounted for USB_CDC Enumeration
R17
100K
GPIO_4
R18
100K
GPIO_5
GPIO_3
R19
100K
DVDD33
GPIO_6
DVDD33
DVDD33
DVDD33
R15
100K
DVDD33
DVDD33
VIN_33
VRF33
GPIO_16
R22
100K
R21
100K
R23
4.7K(NP)
R24
4.7K(NP)
R5
100K
Note:
Y1 is used for accurate w akeup time
R7
100K
U1
RS9113 based Module
GN
D
1
VIN_MOD
49
GPIO_21
81
GPIO_16
28
GPIO_15
29
PDN
58
GPIO_18
82
GPIO_17
84
SDIO_DATA2
26
SDIO_CLK
25
SDIO_DATA3
80
SDIO_DATA1
79
SDIO_CMD
24
SDIO_DATA0
78
USB_VDDP
77
USB_VBUS
16
GND
20
USB_DP
18
USB_ID
19
USB_VDDD
15
GPIO_5
13
NC
46
WURX
2
GN
D
42
RF_OUT_2
32
NC
39
GN
D
33
GN
D
85
RF_OUT_1
37
GN
D
34
GN
D
35
GN
D
36
NC
89
GN
D
38
GPIO_19
21
GPIO_11
8
GPIO_12
98
GN
D
51
GN
D
90
VRF33
53
GPIO_9
7
GPIO_14
9
GPIO_10
6
GPIO_13
71
XTAL_32Khz_N
5
XTAL_32Khz_P
4
VBATT
100
GND
48
NC
56
ULP_GPIO_2
99
RESET_N
74
VDD33
59
JP1
70
JP0
69
BOOTLOAD_EN
41
HOST_SEL_1
55
HOST_SEL_0
60
BBP_LMAC_VDD_12
91
GPIO_8
83
VOUTLDOP3
66
NC
31
USB_DN
17
USB_VDDS
23
SDIO_VDD_18_33
27
GPIO_3
22
GPIO_4
12
GPIO_6
76
GPIO_0
75
GPIO_1
11
GPIO_2
10
GN
D
47
NC
54
GN
D
43
GN
D
45
ULP_GPIO_1
68
HOST_BB_EN
94
ULP_GPIO_0
3
AUX_DAC_OUT
93
JP2
96
JNC
97
GN
D
86
AUX_ADC_IN0
65
BOOT_MODE_0
40
GN
D
44
GPIO_7
30
VOUTLDOP1A
63
VOUTLDOP1
92
USB_VDDA
14
NC
72
EXT_PA_ON
64
GN
D
57
GN
D
87
GN
D
88
GN
D
101
DVDD33
50
NC
61
VRF33
52
ULP_ANAGPI
73
GN
D
67
NC
95
NC
62
DVDD33
R2
1K
RESET_N
R6
100K
C6
20pF(NP)
Y 1
MC-146(NP)
1
4
R3
1K
C7
20pF(NP)
R4
1K
C1
2.2uF
NO POPULATE
without integrated antenna
GPIO_0
GPIO_1
C4
2.2uF
FB9
BEAD
C23
0.1uF
Note:
R15, R21, R22 should be mounted
only w hen ULP not USED
C21
0.1uF
VINMOD
C3
10uF(0805)
ANA3V3
D1
LED
LED Indication
GPIO_16
R8
820E
VDD_EXT
R10
100K
RESET_N
C13
0.1uF
OPTION-1
RESET_N
C14
8.2nF
R12
100K
R9
1M
U2
MAX6415
VCC
5
SRT
4
RESETn
1
GND
2
RESET IN
3
C12
0.1uF
R
11
1M
SW
1
1
2
RESET Circuitry
OPTION-2
Title
Size
Document Number
Rev
Date:
Sheet
of
RS9113 based Module without integrated antenna -SPI
1
1
Rev0.0
VDD_EXT
VDD_EXT
C2
8.2pF
50 Ohm RF line
Redpine Signals Confidential
Z1 , Z2 , Z3 form the tuning network for
matc hing the impedanc e of the A ntenna.
T he values depend upon the layout. I n c as e
tuning network is not implemented Z1
s hould be plac ed as 8 .2 pF as default
ANT1
ANT1
1
ANT2
2
Z2
TBD
Z3
TBD
Tuning Netw ork
Z1
TBD
M ic rowave s witc h is us ed for evaluating the
s tandalone T rans mit/Rec eive performanc e of the
WLA N module by providing direc t c onnec tivity to
Signal generator/A nalyzer through RF c able
J1
MM8430-2610RA1
ANTIN
3
ANTOUT
4
GN
D
1
GN
D
2
GN
D
5
GN
D
6
Place Z1-Z3 Close together
and near to ANT1
Mating Connector Part No::MXHS83QH3000
SPI_MISO
SPI_MOSI
SPI_CLK
SPI_CS
SPI_INTR
SPI_CS
SPI_CLK
VIN_33
SPI_MOSI
SPI_MISO
SPI_INTR
NOTE:
Based on the Host SPI conf iguration, during BOOT UP, SPI Master could be
coming up as GPIO pins.In the wake of this possibility , it may be needed to add a
pull up on the SPI_CS and a pull up (CPOL=1)/pull down(CPOL=0) on the
SPI_CLK. The v alue of pull up/ pull down resistor should f ollow the
recommendations as giv en on the HOST side.
J2
SPI Interface Connector
CD/DAT3
1
CMD
2
VSS1
3
VDD
4
CLK
5
VSS2
6
DAT0
7
DAT1
8
DAT2
9
R6**
C10
10uF(0805)
NOTE:
R6** v alue should be adjusted based
on driv er output impedance and PCB
Trace Impedance,,(33E is Nominal)
Figure 17: SPI mode Interface Schematic