Realtek RTL8100 Programming Manual Download Page 10

 
 

RTL8100 

 

2001/12/10 

Rev.1.0 

 
 

10

3 Initialization 

Though transmit reset and Receive reset can be done individually, there are three steps in the initialization procedure. 

1.  Enable Transmit/Receive (RE/TE in CommandRegister) 

2. Configure 

TCR/RCR. 

3. Enable 

IMR. 

Additional Notes 

This section covers some information on the source code provided. 

1.  This sample code has been developed under Borland C 3.0, and the debugging process was accomplished under Softice 

for DOS. All testing is done under DOS(win98). 

2.  To enable source code debugging under Softice, the compiling/linking process needs to generate a ‘.map. file. Softice 

provide a ‘msym’ program to translate ‘.map’ files to ‘.sym’ files. After the ‘.sym’ file is generated, load the demo 
program with ‘Ldr demo’. 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 Realtek Semiconductor Corp. 
 Headquarters 

 1F, No. 2, Industry East Road IX, Science-based 
 Industrial Park, Hsinchu, 300, Taiwan, R.O.C. 
 Tel: 886-3-5780211  Fax: 886-3-5776047 
WWW: www.realtek.com.tw 

 

Summary of Contents for RTL8100

Page 1: ...2 6 Configuration 8 2 7 Sample Code 9 3 Initialization 10 Additional Notes 10 This document is intended for use by the software engineer when programming for the Realtek RTL8100 series NIC controller...

Page 2: ...on of a packet 28 R CDH CD Heart Beat The same as RTL8029 AS This bit is cleared in the 100Mbps mode 27 24 R NCC3 0 Number of Collision Count Indicates the number of collisions encountered during the...

Page 3: ...mit Status register Also clear the OWN bit in TSD This starts the PCI operation 3 As the data moved into the FIFO meets the early transmit threshold the chip starts to move data from the FIFO to the l...

Page 4: ...ssing a transmit interrupt the following two cases should be managed properly Case 1 More than one interrupt between TOK and when ISR routine called Drivers have to check as many descriptor as possibl...

Page 5: ...S_OWN case 0 return TSDSTATUS_0 return 0 void IssueCMD unsigned char descriptor unsigned long offset descriptor 2 outpdw IOBase TSAD0 offset TxDesc TxHwSetupPtr PhysicalAddress outpdw IOBase TSD0 offs...

Page 6: ...gister CBA keeps the current address of the data moved to the buffer CAPR is then a read pointer which keeps the address of data that the driver had read The receiving packet status is stored in front...

Page 7: ...2 R CRC CRC Error When set indicates that a CRC error occurred on the received packet 1 R FAE Frame Alignment Error When set indicates that a frame alignment error occurred on this received packet 0...

Page 8: ...arly threshold No early FIFO Buffer DMA starts when the whole packet is in the FIFO If an incoming packet is larger than the size of the FIFO 2K RxFIFOOvw will be set but Rx DMA will never start so th...

Page 9: ...CR_BUFE break do RxReadPtr RxBuffer RxReadPtrOffset pPacketHeader PPACKETHEADER RxReadPtr pIncomePacket RxReadPtr 4 PktLength pPacketHeader PacketLength this length include CRC if PacketOK pPacketHead...

Page 10: ...n developed under Borland C 3 0 and the debugging process was accomplished under Softice for DOS All testing is done under DOS win98 2 To enable source code debugging under Softice the compiling linki...

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