Realtek Ameba-D RTL872 D Series, User Manual

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Ameba-D User Manual
User Manual All information provided in this document is subject to legal disclaimers. © REALTEK 2019. All rights reserved.
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3 Memory Protection Unit (MPU)
The KM4 and KM0 processor both have a memory protection unit (MPU) that provides fine grain memory control, enabling applications to
implement security privilege levels, separating code, data and stack on a task-by-task basis. Such requirements are critical in many embedded
applications.
The MPU needs to be programmed and enabled before use. If the MPU is not enabled, the memory system behavior is the same as that no
MPU is present.
The MPU can improve the reliability of an embedded system by:

Preventing user applications from corrupting data used by the operating system

Separating data between processing tasks by blocking tasks from accessing others’ data

Allowing memory regions to be defined as read-only so that vital data can be protected

Detecting unexpected memory accesses (for example, stack corruption)
In addition, the MPU can also be used to define memory access characteristics such as caching and buffering behaviors for different regions.
The MPU sets up the protection by defining the memory map as a number of regions. As Table 3-1 shows, up to eight regions can be defined,
but it is also possible to define a default background memory.
Table 3-1 MPU entries
CPU Secure Region Number
KM4 Non-Secure MPU x8
Secure MPU x4
KM0 Non-Secure MPU x4
3.1 Register Map
Table 3-2 provides the details of the MPU register map. All registers in MPU are addressed at 32-bit boundary. Where the physical size of any
register is less than 32-bit wide, the upper unused bits of the 32-bit boundary are reserved. Writing to these bits has no effect; reading from
these bits returns 0.
Table 3-2 Register map of MPU
Name Address Offset Description
MPU_TYPE 0xE000_ED90 MPU Type Register
MPU_CTRL 0xE000_ED94 MPU Control Register
MPU_RNR 0xE000_ED98 MPU Region Number Register
MPU_RBAR 0xE000_ED9C MPU Region Base Address Register
MPU_RLAR 0xE000_EDA0 MPU Region Limit Address Register
MPU_RBAR_A< n > 0xE000_EDA4 MPU Region Base Address Register Alias ( n = {1, 2, 3})
MPU_RLAR_A< n > 0xE000_EDA8 MPU Region Limit Address Register Alias ( n = {1, 2, 3})
MPU_MAIR0 0xE000_EDC0 MPU Memory Attribute Indirection Register 0
MPU_MAIR1 0xE000_EDC4 MPU Memory Attribute Indirection Register 1
3.2 Register Field Description
3.2.1 MPU_TYPE
The MPU_TYPE characteristics are:

Purpose: The MPU Type Register indicates how many regions the MPU supports for the selected security state.

Usage constraints:

Privileged access is permitted only. Unprivileged access generates a BusFault.

This register is word accessible only. Half-word and byte accesses are unpredictable.

Configurations: This register is always implemented.