Copyright © 2015 Robot Circuits, LLC
13
RCAT-1A Rev A3 Designer’s manual
Serious Power for the Serious Designer
A complete list of all the subsystems on the RCAT™ is presented below:
Subsystem Name
Type
Access Connector
Description
And Associated Jumpers
LED
Dedicated
N/A
Onboard Green/Yellow LED controlled by ports
PL6 and PL7
System Clock
Dedicated
JP1
16MHz Crystal with XTAL1 disconnect via JP1
Extended Static RAM
Dedicated
N/A
A Cypress Semiconductor CY7C1019D-10VXI
RAM chip is provided onboard that makes 128K
bytes of static RAM available to the CPU in two
pages of 64K bytes. Page selection is managed
via dedicated I/O port PJ7. The chip I/O reserves
CPU ports AD0-AD7, A8-A15, and PG0-PG2 for
its exclusive use.
TWI Interface
Bussed
J2
Provides direct access to CPU ports PD0 and
PD1 (SCL/SDA) via J2 pins 8 and 6 respectively.
Resistors R4 and R5 pull these pins up to Vcc as
required by TWI. Two additional pins, J2/7 and
J2/5, provide access to the TWI bus through
bidirectional 3V level shifters for interfacing to
3V TWI devices.
1M-bit serial EEPROM
Bussed
J2
M24M01-RMN6TP serial EEPROM controllable
via CPU or external TWI at J2. See TWI details
above and EEPROM datasheet for details. Chip
write enable (/WC) is directly controlled by port
PD4 on CPU chip. This is not accessible outside
the CPU.
Accelerometer
Bussed/Direct J5, JP23, JP30
The onboard ADXL345 accelerometer chip
Interfaces with the CPU on the TWI bus. This
means that it can also be accessed by the
external TWI connector J2. Jumper JP23 is used
to select the device address and jumper JP30 is
used to enable/disable the device via its /CS
pin. The interrupt outputs (INT1 and INT2) are
brought out to the CPU at PE4 and PE5
respectively. These are also brought out to J5 at
the PE4/PE5 pins. See the accelerometer
section later in this document for schematic and
detailed usage directions.
SPI Interface
Direct
J1
Direct access to Ports PB1, PB2, PB3, RST
J1 configured for use in Serial Peripheral
Interface (SPI) (See ATMega™ Manual for
details)
