WCDMA Multi Evaluation Measurement
R&S
®
CMW-KG4xx/-KM4xx/-KS4xx
577
User Manual 1173.9657.02 ─ 11
Additional information: Phase Discontinuity
Phase discontinuity is the change in phase between two adjacent timeslots. The phase
discontinuity is measured in accordance with the definition of the conformance test
specification 3GPP TS 34.121:
For full-slot measurements (no HSPA channels) a linear best-fit to the phase error
curve in each timeslot (excluding the 25 μs transient periods on either side of the time-
slot boundaries) and an extrapolation onto the slot boundaries yields an estimate of the
phase error at the beginning and at the end of each slot. The phase discontinuity is
defined as the difference between the extrapolated phase at the end of the timeslot
preceding the slot boundary and the extrapolated phase at the start of the timeslot fol-
lowing the slot boundary.
For configurations with HSPA channels a timing offset of one half-slot between a
DPCCH timeslot and a HS-DPCCH timeslot is required (according to 3GPP TS
34.121). Thus the HS-DPCCH slot boundaries are located at the middle of the DPCCH
timeslots, between the first and second half-slot. Using a half-slot measurement, a lin-
ear best-fit is applied to the phase error curve in each half-slot (excluding the 25 μs
transient periods) and extrapolated onto the boundary between the first and second
half-slot. The phase discontinuity is defined as the difference between the extrapolated
phase at the end of the first half-slot and the extrapolated phase at the start of the sec-
ond half-slot.
For additional information refer to
chapter 3.2.6.13, "Common View Elements"
3.2.6.7
Detailed Views: CD Monitor
The code domain monitor displays the Code Domain Power (CDP) and Code Domain
Error (CDE) for all code channels, measured in the "Preselected Slot". The code
domain measurements are not relevant for QPSK-modulated signals (see parameter
General Description
深圳德标仪器
135-1095-0799
