Hardware Reference Manual
CP945FP-12 CompactPCI, RM945FP-12 VME, & RM948 With Embedded Layer 2
Switch, Front Input/Output
DDC No. Rx-URMH 122 Rev A
Issued 5 December 2003
6 of 18
2 Theory Of Operation
The switch architecture is illustrated in the block diagram below. Total port count is achieved by combining two
ZarlinkMDS 108 8 port fabrics via their uplink.
By definition, a Network Switch differs from a hub in that each packet received into the switch is transmitted to the
minimum number of ports. This greatly improves aggregate data rate (i.e., multiple pairs of ports can be involved
in data transfer at a single point in time). As each packet arrives at the switch, both the source and destination
address of the packet are examined. The source is retained and associated with the arrival port as the location of
that device. If the packet is unicast (i.e., destined for a single receiver) and the destination is known, the packet
will only be transmitted to the port associated with the destination address. Since the learning is automatic, no
operator intervention is needed. As attached workstations (or other network capable devices) communicate, their
locations are learned and traffic can be localized to the port.
Isolation*
Magnet
PHY
Isolation*
Magnet
PHY
Isolation*
Magnet
PHY
Isolation*
Magnet
PHY
PHY
PHY
PHY
PHY
Isolation*
Magnet
Isolation*
Magnet
Isolation*
Magnet
Isolation*
Magnet
Buffer
Storage
SRAM
Buffer
Storage
SRAM
PHY
PHY
PHY
PHY
Isolation*
Magnet
Isolation*
Magnet
Isolation*
Magnet
Isolation*
Magnet
Parallel
Port
SROM
Switch Fabric
Switch Fabric
Parallel
Port
SROM
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