Radstone PPC7A Product Manual Download

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PPC7A Product Manual

Functional Description

8-32

Edition

FLASH Control Register (Port 0x086E)

This register provides status and control signals for the Boot sections of the FLASH devices.

When the PPC7A

is reset, this register is reset to reflect the status of the BOOT links (E8, E4 & E7),

after boot software can then override these link settings by writing to bits D5 & D7 in this register.

Status signals BOOT_ALTERNATE, BOOT_FROM_VME & BOOT_RECOVERY show the real link
settings. Signals SELECT_ALTERNATE & SELECT_RECOVERY show what image is really selected.

MSB = D0, LSB = D7

D0:

NVRAM Write Protect

0 = NVRAM is write protected
1 = Writes to NVRAM are enabled

D1:

BOOT_ALTERNATE (reflects the status of user link E8). This bit is read-only.

0 = Link not fitted
1 = Link fitted

D2:

VME_BOOT_MODE (reflects the status of user link E4). This bit is read-only.

0 = Link not fitted
1 = Link fitted

D3:

BOOT_RECOVERY (reflects the status of user link E7). This bit is read-only.

0 = Link not fitted
1 = Link fitted

D4:

Reserved reads ‘0’

D5: SELECT_ALTERNATE

D6: FLASH_CONTROL_WRITTEN

0 = Register not written
1 = Register written

D7: SELECT_RECOVERY

SELECT_ALTERNATE

SELECT_RECOVERY

REA

ELECTED

Main

Recovery

Alternate

Extended

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Summary of Contents for PPC7A

Page 1: ...erutilized and idle equipment along with credit for buybacks and trade ins Custom engineering so your equipment works exactly as you specify Critical and expedited services Leasing Rentals Demos In st...

Page 2: ...PPC7A Product Manual Publication No PPC7A 0HH 1st Edition April 2003 Radstone Technology PLC Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 3: ...rvices concerned The Company reserves the right to alter without notice the specification design price or conditions of supply of any product or service Trademarks The Radstone name Radstone and Power...

Page 4: ...neral Description 2 1 Introduction 2 1 Features 2 2 Functional Overview 2 3 PowerPC Platform 2 3 Processor 2 4 PCI 2 5 Memory 2 6 VMEbus Interface 2 7 Utility I O and Auxiliary Function Bus 2 7 Input...

Page 5: ...11 PMC Connector Pinouts 5 12 J11 and J21 5 12 J12 and J22 5 13 J13 and J23 5 14 PMC Signal Descriptions 5 15 J14 PMC I O 5 16 J24 PMC I O and Partial P2 Option 5 17 P10 PLD Connector Pinout 5 18 P8...

Page 6: ...er Block Transfers 8 15 VMEbus Slave Block Transfers 8 15 Mailboxes 8 15 Semaphore Register 8 16 VMEbus Location Monitor 8 16 VMEbus Interrupts 8 16 VME Bus Errors 8 16 VMEbus Retries 8 17 VMEbus Rese...

Page 7: ...terrupts and Error Reporting 8 35 System Resets 8 35 Machine Check Exception 8 35 System Management Interrupt SMI 8 35 External Interrupt INT 8 36 PCI Interrupts 8 36 PCI Configuration 8 37 Keylock 8...

Page 8: ...whatever the market Communications Local connection of Ultra SCSI Video graphics and VME64 uses PCI as do the two IEEE P1386 1 PMC sites PMCs available directly from Radstone include high performance...

Page 9: ...f configuration installation and power up as simple and user friendly as possible a certain amount of background knowledge on these subjects is assumed In the Functional Description chapter a higher d...

Page 10: ...anual s objectives audience scope structure and conventions safety notices and associated documentation Chapter 2 is a slightly more detailed but still general product description Chapter 3 contains i...

Page 11: ...electrical equipment in such an environment constitutes a definite safety hazard Keep Away From Live Circuits If lethal voltages are present in the equipment do not remove equipment covers In these ci...

Page 12: ...e following European Norms EN55022 CISPR 22 Radio Frequency Interference EN50082 1 IEC80 2 IEC801 3 IEC801 4 Electromagnetic Immunity The product also fulfils EN60950 product safety which is essential...

Page 13: ...nings of 103 106 and 109 respectively The only exception to this is in the description of the size of memory areas when K M and G mean 210 220 and 230 respectively Note When describing transfer rates...

Page 14: ...ment and Data Communications Equipment Employing Serial Binary Data Interchange December 1991 Electronic Industries Association DC20006 USA ANSI EIA TIA 422 B Electrical Characteristics of Balanced Vo...

Page 15: ...Some useful sites are Motorola PowerX data is available through this site http e www motorola com IBM PowerX data is available through this site http www chips ibm com Universe II chip information inc...

Page 16: ...bit 66 MHz PCI interface slots PCI IEEE P1386 1 provides an industry standard high speed 528 Mbytes second local expansion bus designed for graphics high speed communications e g ATM FDDI ISDN etc mu...

Page 17: ...ouble width PMCs Optional PCI expansion bridge on a short PMC card and PMC carrier cards future proof your system design by enabling PCI sub system expansion to add new low cost interface capability a...

Page 18: ...use of industry standard components and buses and a wide range of operating systems As well as providing a detailed hardware design specification the PowerPC Platform also embodies a software mechanis...

Page 19: ...ECFP95 7455 733 32 1 23 9 PowerPC 7410 The PowerPC 7410 is a 32 bit superscalar RISC processor clocked at 500 MHz and above with the following features 64 bit external data bus On chip 32 Kbyte instru...

Page 20: ...ptional mezzanine expansion modules PMCs The PCI mezzanine format also provides 64 I O pins for user definition A range of PMCs are available from Radstone including high performance graphics MIL STD...

Page 21: ...is the left most slot of the P0 PCI backplane For further information about P0 backplanes please contact Radstone directly or talk to your nearest Sales Office Memory System RAM Between 64 and 512 Mb...

Page 22: ...ts general purpose I O and auxiliary functions are implemented through an South bridge bus interface Facilities provided include Parallel printer port Four PC compatible serial interfaces Floppy disk...

Page 23: ...VxWorks bootroms the Boot firmware technology is absorbed into such boot methodology Built In Test PPC BIT probes from the lowest level of discrete on board hardware up to Line Replaceable Unit level...

Page 24: ...roach allows users to implement a verifiable BSP standard and yet not be locked out of using valuable extra features which will adapt the BSP but shorten development times ESP features may be added or...

Page 25: ...features wide temperature range industrial grade devices an integral thermal management layer and incorporates a central stiffening bar for additional strength Cooling is achieved through conduction...

Page 26: ...s are identified by labels at strategic positions You can cross check these against the Advice Note provided as a separate note with your delivery On the outside of the shipping box and the antistatic...

Page 27: ...is also attached to the printed wiring board The Ethernet number has the form XX XX XX XX XX XX for instance 00 80 8E 00 50 93 Inspection 1 Visually inspect the board for any damage and loose or dislo...

Page 28: ...nfiguration of links on the PPC7A The board is delivered with push on jumper links but for more rugged or military applications link pins must be connected using wire wraps Figure 4 1 Link Locations A...

Page 29: ...n the following pages Note If you are about to install your board and power up for the first time leaving your board in the default configuration as above will enable board operation to be proved prio...

Page 30: ...to program boot code to the FLASH devices To program the boot code into the FLASH devices the VME master will need to program up both the Universe and also the GT 64260 to allow a window from VME int...

Page 31: ...of the links are fitted the PPC7A boots from the alternate boot image After boot time the link setting can be software overridden to select the different images E7 E8 FUNCTION Out default Out default...

Page 32: ...e decoded as follows BOARD ID E10 E12 E2 E11 15 default Out Out Out Out 14 Out Out Out In 13 Out Out In Out 12 Out Out In In 11 Out In Out Out 10 Out In Out In 9 Out In In Out 8 Out In In In 7 In Out...

Page 33: ...15 No E 0xE000 0000 None 16 No F 0xF000 0000 None Note Any change to the Board ID links will require the hardware registers to be relearned if BIT is not to fail VMEbus Interface Configuration Severa...

Page 34: ...following table shows the function of the connectors on the PPC7A CONNECTOR FUNCTION P1 VMEbus P2 VMEbus P0 PMC site 1 I O J11 J12 J14 PMC site 1 J21 J22 J24 PMC site 2 J25 J26 I O expansion P8 RISCW...

Page 35: ...2 GND DS1 BR0 SYSRESET NC 13 NC DS0 BR1 LWORD GA2 14 GND WRITE BR2 AM5 NC 15 NC GND BR3 A23 GA3 16 GND DTACK AM0 A22 NC 17 NC GND AM1 A21 GA4 18 GND AS AM2 A20 NC 19 NC GND AM3 A19 NC 20 GND IACK GND...

Page 36: ...A RST SCSI 5V GPIO5 COM5_RXD 14 GND MSG SCSI D16 GPIO6 COM5_CTS 15 COM4_RXD_B SEL SCSI D17 GPIO7 COM3_TT_A 16 GND C D SCSI D18 GPIO8 COM3_TT_B 17 COM4_CTS_A REQ SCSI D19 GPIO9 COM3_ST_A 18 GND I O SCS...

Page 37: ...IO_19 14 GND MSG SCSI D16 GPIO6 PMC2_IO_21 15 PMC2_IO_23 SEL SCSI D17 GPIO7 PMC2_IO_22 16 GND C D SCSI D18 GPIO8 PMC2_IO_24 17 PMC2_IO_26 REQ SCSI D19 GPIO9 PMC2_IO_25 18 GND I O SCSI D20 GPIO10 PMC2_...

Page 38: ...Y 19 GPIO11 WPROT PERROR 20 GPIO12 TRK0 SELECT 21 GPIO13 INDEX AUTOFD 22 GPIO14 DENSEL ERR 23 GPIO16 GPIO16 ACGAME3 INIT 24 GPIO17 GPIO17 ACGAME4 SLCTIN Notes There is no connection to GPIO15 of the s...

Page 39: ...to use the bus D00 to D31 Data Bus These are used to transfer data between masters and slaves and status ID information from interrupters to interrupt handlers DS0 DS1 Data Strobe 0 1 These are used...

Page 40: ...tor power Supplies power for external SCSI bus terminators Rated at 1 Amp MOUSE_CLK Mouse Clock Clock drive for mouse MOUSE_DATA Mouse Data Mouse data line KBD_5V Keyboard 5V Supplies power for the ke...

Page 41: ...REN Global FLASH write enable EXT_RESET External Reset Hard Reset EXT_ABORT External Abort Soft Reset USBP0 USBP0 USB interface Port 0 USBP1 USBP1 USB interface Port 1 RED GREEN BLUE VSYNC HSYNC VGA p...

Page 42: ...GND 11 PMC2_IO_52 PMC2_IO_51 PMC2_IO_61 PMC2_IO_58 PMC2_IO_57 GND 12 PMC1_IO_30 PMC1_IO_29 PMC1_IO_28 PMC1_IO_27 PMC1_IO_26 GND 13 PMC1_IO_35 PMC1_IO_34 PMC1_IO_33 PMC1_IO_32 PMC1_IO_31 GND 14 PMC1_IO...

Page 43: ...O_26 GND 10 PMC1_IO_35 PMC1_IO_34 PMC1_IO_33 PMC1_IO_32 PMC1_IO_31 GND 11 PMC1_IO_40 PMC1_IO_39 PMC1_IO_38 PMC1_IO_37 PMC1_IO_36 GND 12 PMC1_IO_45 PMC1_IO_44 PMC1_IO_43 PMC1_IO_42 PMC1_IO_41 GND 13 PM...

Page 44: ...erates a Soft Reset See the Resetting the PPC7A section in Chapter 8 for more details NC No connection TCE6 TCE7 GT 64260 Timer counter enable TCT6 TCT7 GT 64260 Timer counter terminal count 3 3V Thes...

Page 45: ...10 NC 11 GND 12 NC 13 CLK 14 GND 15 GND 16 GNTA 17 REQA 18 5V 19 VIO 20 AD31 21 AD28 22 AD27 23 AD25 24 GND 25 GND 26 C BE3 27 AD22 28 AD21 29 AD19 30 5V 31 VIO 32 AD17 33 FRAME 34 GND 35 GND 36 IRDY...

Page 46: ...9 AD18 30 GND 31 AD16 32 C BE2 33 GND 34 IDSELB 35 TRDY 36 3 3V 37 GND 38 STOP 39 PERR 40 GND 41 3 3V 42 SERR 43 C BE1 44 GND 45 AD14 46 AD13 47 M66EN 48 AD10 49 AD08 50 3 3V 51 AD07 52 REQB 53 3 3V 5...

Page 47: ...AD56 23 AD55 24 AD54 25 AD53 26 GND 27 GND 28 AD52 29 AD51 30 AD50 31 AD49 32 GND 33 GND 34 AD48 35 AD47 36 AD46 37 AD45 38 GND 39 V I 0 40 AD44 41 AD43 42 AD42 43 AD41 44 GND 45 GND 46 AD40 47 AD39...

Page 48: ...Reset Driven low to reset the PCI bus TRDY Target Ready Driven low by the current target to signal its ability to complete the current data phase PERR Parity Error Driven low by a PCI agent to signal...

Page 49: ...5 26 PMC1_IO_26 27 PMC1_IO_27 28 PMC1_IO_28 29 PMC1_IO_29 30 PMC1_IO_30 31 PMC1_IO_31 32 PMC1_IO_32 33 PMC1_IO_33 34 PMC1_IO_34 35 PMC1_IO_35 36 PMC1_IO_36 37 PMC1_IO_37 38 PMC1_IO_38 39 PMC1_IO_39 40...

Page 50: ...O_23 Z15 24 PMC2_IO_24 D16 25 PMC2_IO_25 D17 26 PMC2_IO_26 Z17 27 PMC2_IO_27 D18 28 PMC2_IO_28 D19 29 PMC2_IO_29 Z19 30 PMC2_IO_30 D20 31 PMC2_IO_31 D21 32 PMC2_IO_32 Z21 33 PMC2_IO_33 D22 34 PMC2_IO_...

Page 51: ...onnector Pinout P8 is the RISCWatch connector allowing the connection of software debugging tools that use the processor s JTAG port to control the operation of the processor PIN NO SIGNAL PIN NO SIGN...

Page 52: ...t CHECKKSTOP Processor Checkstop output GND Signal ground For more information on JTAG see Chapter 8 EST Emulator Connection PIN NO SIGNAL DESCRIPTION 1 TDO_CPU Processor JTAG Test Data Out 2 QACK_IN...

Page 53: ...DS3 are mounted on the front panel DS1 is yellow DS2 is red and DS3 is green See the Software Programmable LEDs section in Chapter 9 for more details Switches A momentary action toggle switch is fitte...

Page 54: ...PPC7A Product Manual Front Panel 6 2 Figure 6 1 PPC7A Front Panel 1st Edition Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com...

Page 55: ...N4 3 99 contains the fitting instructions PMCs ordered with a PPC7A can be supplied factory fitted by Radstone if required It may be necessary to install driver software or implement other firmware co...

Page 56: ...The lower link configures the Interrupt Acknowledge IACK daisy chain When a slot position is not occupied by a board and there are boards further down the daisy chain connect the appropriate In signa...

Page 57: ...in the rack or enclosure Note The default link configuration requires the board to be inserted into system slot 1 2 Push the board firmly home to ensure the connectors mate properly with the backplane...

Page 58: ...the PPC7A This terminal will use the serial signals on COM1 Cables supplied by Radstone permit direct connection to a terminal without use of a null modem Alternatively a PMC9100 PMC2 9100 graphics P...

Page 59: ...ram BIT is described in the PPC BIT Release Notes publication number RT5111 The Boot firmware is described in the PPC Boot Firmware Manual publication number RT5078 VxWorks is described in the VxWorks...

Page 60: ...ed by the Operating System s Hardware Independence mechanism BSP HAL residual data etc and not directly by application software 3 If a standard operating system is not being used then it is recommende...

Page 61: ...write through or write back modes Operation at speeds up to 266 MHz through a dedicated L3 cache bus interface Can caches memory accesses in the address range 0x0000 0000 to 0x4000 0000 i e SDRAM Ent...

Page 62: ...back modes Operation at speeds up to 266 MHz through a dedicated L2 cache bus interface Can caches memory accesses in the address range 0x0000 0000 to 0x4000 0000 i e SDRAM Entries in write through m...

Page 63: ...ard reset signal pin C1 Hard reset all devices If System Controller SW_LRST bit VCSR bit Hard reset excluding VMEbus Interface No Software Events SW_SYSRESET bit Hard reset if System Controller If Sys...

Page 64: ...t reset signal pin 11 Software Events HOT_RESET bit in ISA bridge The front panel soft reset switch may be disabled under software control or by fitting hardware jumper E14 The standard boot firmware...

Page 65: ...the size and number of banks of SDRAM and the appropriate number of wait states to match the SDRAM speed This is done by the standard Boot firmware The size of the SDRAM may be checked by reading the...

Page 66: ...T_ALTERNATE and E8 BOOT_RECOVERY links To write to this area Links E5 Overall FLASH Write Enable and E9 System FLASH Write Protected need to be fitted Alternate BOOT This area would normally contain a...

Page 67: ...VME by default The VME master will use these registers to set up windows onto the PCI bus from VME The GT64260 will have its register set available at address 0x1400 0000 The PowerPC s boot FLASH can...

Page 68: ...3 3V via a 4 7 k pull up resistor TDI 3 3V via a 4 7 k pull down resistor The JTAG signals from P8 connect into the CPU JTAG signals They have the following terminations TCK 3 3V via a 1 k pull down...

Page 69: ...PPC7A has BUSMODE2 to BUSMODE4 wired to 1 0 0 respectively This effectively interrogates the PMC site as to whether it has a PCI compliant card fitted The response from the PMC is returned on BUSMODE...

Page 70: ...ted as a 64 bit PCI bus running at up to 66 MHz This gives a burst rate up to 528 Mbytes second between PCI agents The PCI bus structure of the PPC7A is shown below Memory PCI Bridge The Memory PCI Br...

Page 71: ...nously or 14 Mbytes second asynchronously Connection to the SCSI bus is made through the P2 connector The pinout is given in Chapter 5 The PPC7A has an on board active SCSI terminator which may be ena...

Page 72: ...ng a PMCPCI card allows the PCI bus to come out to the backplane via P0 must be fitted in PMC slot 1 South Bridge Peripheral Components The South Bridge connected to the PCIbus contains a floppy disk...

Page 73: ...ocal address to a different address on the VMEbus allowing any local address to access any VMEbus address The start and end addresses of the A32 A24 and A16 PCI slave images may be set on any 64 Kbyte...

Page 74: ...old ownership of the VMEbus This method can be used in combination with VMEbus LOCK cycles to guarantee exclusive access to a VMEbus resource The VMEbus slave images may be programmed to generate lock...

Page 75: ...owledge cycle The Universe captures the status ID and then raises an interrupt on the PCI bus No further VMEbus interrupts are handled on that level until the processor reads the status ID and re arms...

Page 76: ...ee the VMEbus Interface Configuration section in Chapter 4 for the default options Watchdog Timers The PPC7A contains a Maxim 706 microprocessor supervisory circuit with a watchdog timer Once enabled...

Page 77: ...other 8 LEDs are all surface mounted on the back of the PCB DS16 DS17 DS18 and DS19 are Ethernet status LEDs for channel 1 and DS20 DS21 DS22 and DS23 are for channel 2 The default functions of these...

Page 78: ...xtended Mode WO 0410 to 043F South Bridge DMA Scatter Gather 0481 to 048B South Bridge DMA High Pages 04D0 and 04D1 South Bridge Edge Level Control 04D6 DMA 2 Extended Mode WO 0804 Memory Configuratio...

Page 79: ...ng register descriptions the bit significance is shown in big endian mode i e from the viewpoint of the PowerPC 750 programmer Memory Configuration Register Port 0x0804 This register provides informat...

Page 80: ...ze 0 64 Mbytes 1 128 Mbytes 2 256 Mbytes 3 Reserved D2 to D4 Reserved D5 to D7 FLASH banks and size configuration D5 D6 D7 DEVICE SIZE NO OF BANKS MBYTES 0 0 0 256 M bit 1 128 0 0 1 128 M bit 1 64 0 1...

Page 81: ...power fuse MSB D0 LSB D7 D0 Hardware ID0 see the Motherboard Type Register for details D1 SCSI_FUSE_GOOD 0 SCSI fuse bad 1 SCSI fuse good Note This is a re settable fuse that re engages when the over...

Page 82: ...II Fitted 0 Not fitted 1 Fitted D1 Reserved always reads 0 D2 COMs 3 to 6 Fitted 0 Not fitted 1 Fitted D3 USB Fitted 0 Not fitted 1 Fitted D4 LPT Fitted 0 Not fitted 1 Fitted D5 and D6 Cache Speed D5...

Page 83: ...Powered by onboard power supply 1 Power from taken from 3 3V pins on VME connectors D6 and D7 SCSI clock speed D6 D7 SPEED MHZ 0 0 Reserved 0 1 40 1 0 80 1 1 Reserved Key Lock Register Port 0x0818 Thi...

Page 84: ...s 8Kbytes D4 DS11 yellow 0 LED off OFFLINE High 1 LED on OFFLINE Low D5 DS13 and DS1 Yellow 0 LED on SYSFAIL Low 1 LED off SYSFAIL High D6 DS12 and DS2 Red and S YSFAIL P0 B1 signal 0 LED off 1 LED on...

Page 85: ...2 selects which interface is used for COM3 0 RS232 1 RS422 D3 COM3_TX_EN when enabled allows all of the COM3 interface buffers 0 Disabled 1 Enabled D4 COM4_CLK_EN this bit enables the TSCLK4 signal ou...

Page 86: ...Register Port 0x0828 This register controls the watchdog resets features of the PPC7A MSB D0 LSB D7 D0 Last reset was a watchdog 0 Normal reset 1 Last board reset was caused by a watchdog timeout D1...

Page 87: ...SB D0 LSB D7 D0 to D2 Number revision of hardware build state 1 Revision 1 2 Revision 2 3 Revision 3 All other values are Reserved D3 to D7 Letter revision of hardware build state 0x0 Revision A 0x1 R...

Page 88: ...0 Link fitted 1 Link not fitted D5 E10 GA2 0 Link fitted 1 Link not fitted D6 E8 GA1 0 Link fitted 1 Link not fitted D7 E4 GA0 0 Link fitted 1 Link not fitted Note Bits D4 D5 D6 and D7 are also connec...

Page 89: ...TYPE 0 Reserved 1 ECC D3 ECC 0 ECC not fitted 1 ECC fitted D4 PLL1 see table below D5 PLL0 see table below PLL2 PLL1 PLL0 BUS SPEED MHZ 1 1 1 Reserved 1 1 0 Reserved 1 0 1 Reserved 1 0 0 133 0 1 1 Res...

Page 90: ...WREN signal 0 Signal not active Pin high 1 Signal active Pin low D2 FLASH BOOT write enable link 0 link not fitted 1 link fitted D3 FLASH USER write enable link 0 link not fitted 1 link fitted D4 Alwa...

Page 91: ...selected MSB D0 LSB D7 D0 NVRAM Write Protect 0 NVRAM is write protected 1 Writes to NVRAM are enabled D1 BOOT_ALTERNATE reflects the status of user link E8 This bit is read only 0 Link not fitted 1 L...

Page 92: ...0x0F PPC7A 745x 0x10 PPC7FW MPC7410 with Firewire All others patterns mean the board is not a PPC7A Last Reset Source Port 0x2 This register provides information about what caused the last reset MSB...

Page 93: ...0x6 MSB D0 LSB D7 D0 to D7 Reads 0x43 C Port 0x7 MSB D0 LSB D7 D0 to D7 Reads 0x37 7 Status Registers on CS1 These registers are accessed via the GT64260 CS1 address window see GT64260 for more infor...

Page 94: ...pter Machine Check Exception The South Bridge can be configured the signal NMI on certain conditions The hardware on the PPC7A routes this signal to the CPU as the MCP Machine Check interrupt The Sout...

Page 95: ...carrier These are connected to the PIRQ inputs of the interrupt controller The PIRQ inputs may be routed to any IRQ that is set to level sensitive mode The interrupt routing follows the recommendation...

Page 96: ...device number mapping for the PCI bus 0 attached to the GT64260 is as follows DEVICE NO FUNCTION 0 to 15 Not implemented 16 53C860 SCSI controller 17 Not implemented 18 South bridge 19 Not implemente...

Page 97: ...you may also register support requests using the Technical Support Request Form available through the Radstone web site at http www radstone co uk This form looks like Your query will be logged on Rad...

Page 98: ...ck that the cable stub length is less than 10 cm You are also recommended to locate the PPC7A at one end and enable the bus terminator by fitting link E13 If you want to use the PPC7A somewhere other...

Page 99: ...ce Local resources EMC regulatory compliance and safety Power requirements Reliability Mean Time Between Failures Environmental specifications for both build levels General dimensions Weight Ordering...

Page 100: ...O BLT D16 D16 RMW D16 BLT D32 D32 RMW D32 BLT D32 UAT D64 MBLT Interrupt Handler D08 O IH 1 7 Interrupter I 1 7 VMEbus Arbiter SGL RRS PRI BCLR generation VMEbus Requester ROR RWD Early BBSY release B...

Page 101: ...4 bit 66 MHz SCSI 8 bit fast Ultra SCSI via the P2 connector Ethernet 2 off Ethernet 10 100BaseT via the P2 connector PMC Slots Air cooled Two 5V 32 bit IEEE P1386 1 compliant slots with front panel a...

Page 102: ...f 3500 mA for the 128 Mbyte SDRAM version and 3500 mA for the 256 Mbyte SDRAM version Note When using PMCs ensure that they do not cause the specified maximum supply current to be exceeded especially...

Page 103: ...itted PMCs The failure rates used in this calculation are based on MIL HDBK 217F Notice 1 parts count method with commercial or non military quality level Where a component did not comply with the MIL...

Page 104: ...ions The PPC7A is constructed on a multi layer double Eurocard and conforms to the dimensions specified in the ANSI VITA 1 1994 specification The dimensions shown below are in millimetres with inches...

Page 105: ...Mouse GPIO 6 128MB USB Parallel 7 128MB Keyboard Mouse Parallel 8 256MB USB GPIO 9 256MB Keyboard Mouse GPIO A 256MB USB Parallel B 256MB Keyboard Mouse Parallel MEMORY 0 Reserved 1 128MB 2 3 Reserve...

Page 106: ...options PMCEXT Ethernet interface 1 and 2 only 100BaseTX Fast Ethernet interface PMCATMF ATM interface 1 to 4 155 Mbps ATM adapter for OC 3 fiber networks PMCF1 FLASH memory 1 to 5 High capacity FLAS...

Page 107: ...e Backplane Transition Module for the PPC7A is the P25X606 illustrated below Compatible Rear I O modules are shown in parenthesise For installation instructions refer to the I O Module Installation Gu...

Page 108: ...T P5 Parallel Keyboard Mouse 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 GND RED GREEN BLUE HSYNC VSYNC J3 Analogue Monitor GND GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 2...

Page 109: ...d COM4 terminated Ethernet Options 1 1 x Ethernet 2 2 x Ethernet Video Comms Options 1 Video COM 1 2 5 RS232 COM3 RS232 422 No COM6 2 No Video COM 1 2 5 6 RS232 COM 3 4 RS232 422 Build Level 1 Level 1...

Page 110: ...T5116 BCS Background Condition Screening CR CSR Configuration ROM Control and Status Register LRU Line Replaceable Unit PPC7A Radstone s PowerPC based processor card The PPC7A is based on the PowerPC...

Page 111: ...3 E ECC 8 6 8 30 EMC 7 3 Regulatory Compliance A 4 Environment A 5 EST Emulator Connection 5 19 Ethernet Controller 8 12 F Floppy Disk Controller 8 13 Front Panel 6 1 Functional Overview 2 3 H Heatsi...

Page 112: ...8 5 Watchdog 8 5 Revision State 8 28 S Safety A 4 Notices 1 4 SCSI Processor 8 12 Terminator 8 12 8 22 9 2 Semaphores 8 16 Serial I O 8 13 Software Support 2 8 System Controller 8 14 T Technical Help...

Page 113: ...uipment Have surplus equipment taking up shelf space We ll give it a new home Learn more Visit us at artisantg com for more info on price quotes drivers technical specifications manuals and documentat...

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