RadiSys EPC-26A/27, Manual

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Page B1
B B
Appendix B:
Chip Set & I/O Map
The following defines the I/O addresses decoded by the EPC. It does not define
addresses that might be decoded by EXMs.
First (8-bit) DMA controller:
PicoPower Redwood chip set emulating 8237 of PC/AT
I/O Addr Functional group Usage
000 DMA Channel 0 address
001 Channel 0 count
002 Channel 1 address
003 Channel 1 count
004 Channel 2 address
005 Channel 2 count
006 Channel 3 address
007 Channel 3 count
008 Command/status
009 DMA request
00A Command register (R)
Single-bit DMA req mask(W)
00B Mode
00C Set byte pointer (R)
Clear byte pointer (W)
00D Temporary register (R)
Master clear (W)
00E Clear mode reg counter (R)
Clear all DMA req mask(W)
00F All DMA request mask
First Interrupt controller:
PicoPower Redwood chip set emulating 8259 of PC/AT
I/O Addr Functional group Usage
020 Interrupt controller 1 Port 0
021 Port 1
82C42 controller:
I/O Addr Functional group Usage
ED Data register
EC Index register