Radio Shack TRS-80 Technical Manual Download | Manualshive

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Summary of Contents for TRS-80

Page 1: ...FOR RADIO SHACK SERVICE CENTERS TRS 80 Technical Manual Theory Parts List Schematics CUSTOM MANUFACTURED IN U S A BY RADIO SHACkHa DIVISION OF TANDY CORPORATION...

Page 2: ...formation contained herein While every pre caution has been taken in the preparation of this book the publisher assumes no responsibility for errors or omissions Neither is any liability assumed for d...

Page 3: ...6 CPU Control Group 7 Control Group Bus 7 Address Decoder 8 System RAM 11 Video Divider Chain 13 Video RAM Addressing 16 Alphanumeric Format 16 Video Processing 17 Keyboard 23 Input and Output Port 2...

Page 4: ...e the CPU is now playing games in the video memory who cares about the tape The CPU operates at about 2 MHz therefore digital screw ups seem instantaneous Remember that the CPU is the work horse and t...

Page 5: ...E re O re u o CD v CO o 09 co cc 03 3 zi I CM in in 1 CC LU J Sfc O 3 0 OT...

Page 6: ...S are present The keyboard is located from address 3800 to 380F The video display is located from 3C00 to 3FFF The RAMs start at 4000 and depending on how much RAM is in the system can extend down to...

Page 7: ...puts are low The NOT circles at the input immedi ately tell you that this gate is looking for a signal that is low to cause an output that is high Had the gate been drawn correctly then it would not h...

Page 8: ...U ADDRESS LINES There are system outputs of the microprocessor labeled A0 through A15 that start the address bus Since these lines must go to ROM RAM the keyboard and the video RAM they must be buffer...

Page 9: ...Z40 th e RD Read output Pin 4 of Z23 is tied to pin 19 MREQ Memory Request of the CPU Therefore when pins 19 and 21 of Z40 go low at the same time an RD out put is generated Notice the backward symbol...

Page 10: ...of the hex code in the decoding scheme and handle the selection of all the memories In the binary columns you can see that instead of using two hex digits which is eight binary lines we can ignore two...

Page 11: ...a r C3 in 2 a...

Page 12: ...rom ROM to CPU Notice in Figure 3 ROMA is also attached to pin 9 of NAND gate Z74 A low on pin 9 will cause a resulting high at pin 8 Z74 pin 8 is tied to Z73 pin 9 Z73 pin 8 passes a high to Z74 pin...

Page 13: ...ars all screwed up How can the CPU address a minimum of 4K of RAM using only seven address inputs The answer to that very good question is multiplexing The address from the CPU is multiplexed into the...

Page 14: ...to buffer Z67 pin 14 Pin 13 of Z67 passes CAS to pin 15 of all eight RAMs On the negative transition of CAS the high order addresses A6 through A1 1 will be loaded in the column section of each RAM T...

Page 15: ...64 character mode first Since MODESEL is high pin 3 is shorted to pin 4 of Z43 Pins 6 and 10 are shorted to pins 7 and 9 Remem ber a multiplexer is an electronic equivalent of a multi pole double thr...

Page 16: ...UJ M 1 J O J to c E o J C o o 3 a c LO 3 O CC M o cc r r 3 oa Z a CM cs 03 00 00 00 tf 1 in m in in CM M M N IM M M rv 1 U S i LU CM P CM u 1 C 3 s 1 t h _I o a CO O a a J m u a LU LL CJ in M CM M X...

Page 17: ...n of the counter chain Pin 12 Output A 1 Pin 9 Output B Pin 8 Output C 1 Pin 11 Output D 1 HORIZ PART OF Z6S 12 14 660 0Hz Figure 6 Divider Chain Block Diagram Upon the next negative transmission of t...

Page 18: ...video RAM The CPU only takes charge when it needs to You can see on the display screen when the CPU robs the counter chain of video RAM control Ever notice black streaks all over the screen while grap...

Page 19: ...ider chain input condi tioning logic This signal goes low every six dot cycles see Figure 5 for latch timing On the rising edge of latch low to high transaction ASCII data in RAM is transferred to the...

Page 20: ...inputted at pins 8 10 and 11 This three bit input selects the row position of the addressed dot pattern Z29 outputs five dots at one time Since each character consists of seven rows of five dots the c...

Page 21: ...that define the video portion of the screen not in boundary space upper lower left or right Once all three restrictions are met the dot data is parallel loaded into the register NAND gate Z26 insures...

Page 22: ...play After the horizontal signal is phase shifted the horizontal pulse must be shaped C21 and R43 form a differentiation network which creates a smaller pulse of known width from the shifted HDRV sign...

Page 23: ...Z o N E o o cc Hi o z V a X d rn m cz IZZ O c ZD 1CO z N CO z GL in N 03 CO z in N O z El in N 3 o c 00 0 L 3 01 in z in N in 21...

Page 24: ...the black level Voltage below this level is blacker than black and is known as sync level Voltage above 1 23 volts can be called the white level Normally the black level stays at 1 23 until the sync...

Page 25: ...for the CPU The Z 80 CPU can access up to 256 output input ports In the TRS 80 system we only use one The cassette recorder is the only port used Its address is FF in hex Ports are accessed using onl...

Page 26: ...r this output function is software controlled Z59 is used to store data from the CPU and it builds the output waveform using CPU data CPU data under software control is applied to latch Z59 on pins 4...

Page 27: ...This signal called CASSIN is tied to capacitor C24 and resistor R67 at the input of the audio processor section Z4 pins 1 6 and the output pin 5 form an active filter This part of the circuit is used...

Page 28: ...p flop is said to be set If pin 8 is low and pin 1 1 is high the flip flop is reset The flip flop is being set by cassette data and reset by OUTSIG Z44 monitors the status of Z24 under command from IN...

Page 29: ...closed C8 filters the voltage and the net result is 20 volts or so applied to Q6 and to regulator Z2 Figure 13 shows a simplified dia gram of the internal circuitry in a 723 regulator chip The Figure...

Page 30: ...17 volts AC at J1 pins 1 and 3 Full wave rectifier CR8 recti fies the AC When S1 is closed about 7 VDC is passed through the switch contacts and is filtered by C9 The power supply for Z1 and the curr...

Page 31: ...t is tied to pin 18 of Z1 Z2 and Z3 A12and A13 s leads go to the A0 and A1 inputs to decoder Z4 Z4 is an addition to the address decoder network on the main Board When A12 and A13 is 00 pin 1 of Z4 go...

Page 32: ...0052 C37 0 1 iF 10 12V Disc 1500052 C38 0 1 pF 10 12V Disc 1500052 C39 0 1 iF 10 12V Disc 1500052 C40 0 1 iF 10 12V Disc 1500052 C41 0 1 iF 10 12V Disc 1500052 C42 22 iF 16V Electrolytic Radial 150005...

Page 33: ...R42 1 0 Megohm 1 4W 5 4704102 R43 10 K 1 4W 5 4704068 INTEGRATED CIRCUITS R44 10 K 1 4W 5 4704068 R45 470 K 1 4W 5 4704097 Z1 723 DIP Voltage Regulator 3100001 R46 910 ohm 1 4W 5 4704046 Z2 723 DIP Vo...

Page 34: ...RIPTION NUMBER 3102011 Z69 74LS74 Dual D Positive Edge Trigger ed 3102023 Flip Flop with Preset and Clear 3102015 3102022 Z70 74LS74 Dual D Positive Edge Triggered 3108001 Flip Flop with Preset and Cl...

Page 35: ...8 ROM 450ns ROM C 3108015 I C 74LS42 BCD to Decimal Decoder 3102036 KB1 DS5300 53 Key 2 Shot Key caps 5100013 RESISTORS R1 4 7 K 1 4W 5 R2 4 7 K 1 4W 5 R3 4 7 K 1 4W 5 R4 4 7 K 1 4W 5 R5 4 7 K 1 4W 5...

Page 36: ...sociated with the CS read not chip select pins for each device This added circuitry uses spare gates on the CPU Board Figure 14 shows the circuitry differences The second Board level that used Intel E...

Page 37: ...National ROMs Be careful when identifying the different Board levels The two wire modifications associated with National ROMs are shown in Figure 15 Notice that only two wires are switched around The...

Page 38: ...23 3 22 i 4 21 5 20 i 6 19 1 7 18 8 17 3 9 16 3 10 15 9 11 14 J I 12 13 1 A7 Vcc A6 A8 A5 A9 A4 CS A3 CS A2 A10 A1 A11 A0 08 01 07 02 06 03 05 GND ROM B 04 24 2 23 1 3 22 1 i 4 21 5 20 6 19 5 7 18 8 1...

Page 39: ...ON KEYBOARD PCB IT72 74LS3671 FLYING LEAD CRI POWER INDICATOR HP 5082 4850 FLYING LEAD SPARE GATE Figure 17 TRS 80 Schematic Sheet 1 37...

Page 40: ...LB4 LB5 A6 A5 A4 A3 A2 Al AO RSI 729 CS RS2 ttj RS3 MCM6670P DO DI D2D3D4 A7 A6 10 Z26 74LS20 226 74LS20 mr 12 13 C2 4 10 5 04 16 l 2_ II 0 2C2 IC2 2CI ICI 2C0 ICO 28 74 LSI 53 Y2 Yl V OS 12 l4 ABC0E...

Page 41: ......

Page 42: ...FORT WORTH TEXAS 76102 CANADA BARRIE ONTARIO L4M 4W5 TANDY CORPORATION AUSTRALIA BELGIUM U K 280 316 VICTORIA ROAD PARC INDUSTRIEL DE NANINNE BILSTON ROAD WEDNESBURV RYOALMERE NSW 2116 5140 NANINNE W...

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