Radio Shack TRS-80, Service Manual, Page: 20 / 44

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The MC6847 (VDG) has access to the RAM dur-
ing the low portion of the E clock. Also during
the low portion of E, the signal AS is used to
latch the address lines in the latch (U2). During
the high portion of E, all CPU address and data
lines are valid and any accesses to the RAM or
ROM occur during this time.
The signal window is used for two purposes.
The first usage is to gate the write signal. The
2K x 8 static RAM requires setup and hold time
on the address and data line, during a write
cycle. The address and data lines are both valid
for the high portion of the E clock. By gating
the write pulse with window, a safety margin is
created, so that the write pulse will never go
low while the address or data is changing.
The second usage of the signal window is for
synchronization of the VDG and the CPU. The
two devices must be synchronized to allow
both the CPU and the VDG to use the system
RAM with no conflict. This has been accom-
plished in the MC-10 by forcing the VDG to
latch data at the end of the low portion of the E
clock. To do this, low transition of the signal
HS* is only allowed to happen during the active
portion of the signal window. If HS* occurs dur-
ing the window, the latching of data will occur
at the end of the low portion of the E clock.
RAM
The MC-10 uses two 2K x 8 static RAM chips for
a total internal memory of 4K. The RAM chips
receive their address lines from either the
MC6847 (VDG) or the CPU. This switching is
accomplished by tri-state buffers which are
controlled by the MS* line. The individual RAM
chip is selected by VA11, the 12th address line,
and since the OE* input is grounded, one RAM
is always enabled. The WE* line is generated by
the CPU address decoding logic, and is high
except when the CPU is writing to RAM.
MODULATOR
The outputs from the MC6847 are connected
directly to the modulator. The modulator unit is
built around the MC1372. This is a linear inte-
grated circuit which is designed to interface to
the MC6847 and produce an RF output for con-
nection to the TV. Figure 6 shows a block dia-
gram of the MC1372 chip.
The 3.579545 MHz crystal and associated com-
ponents are connected between pins 1 and 2.
This provides the color burst frequency and the
main clock for the MC-10. The duty cycle input
is left unconnected to produce a 50% duty
cycle clock.
The other inputs to the MC1372 are the lumi-
nance input, øA, øB, and the color reference
voltage input. All of these inputs are connected
directly to the MC6847 chip.
The chroma modulator output is filtered by an
R-C network between pins 8 and 10 of the
MC1372. Also the 4.5 MHz frequency modulated
sound signal is AC coupled in at pin 10. The
sound input to the modulator is used to fre-
quency modulate the 4.5 MHz oscillator com-
posed of Q1 and the associated circuitry.
The channel selection for the modulator is per-
formed by the tank circuit between pins 13 and
14 of the MC1372. This circuit allows the RF
output to be switched from channel 3 to 4 by an
external switch input.
The final RF output of the modulator is avail-
able at pin 12 of the MC1372. However, before
this signal is connected to the output jack, a
vestigial sideband filter must be used to sup-
press unwanted harmonics of the signal. This
filter is shown in the schematic as the thirteen
passive components before the RF output.
Figure 6. MC1372 Block Diagram
11
4 3 7 6 13 14
5 9 12
10
8
2
1
CHROMINANCE
INPUT
CHROMA
MODULATOR
OUTPUT
RF
MODULATOR
OUTPUT
LUMINANCE
INPUT COLOR B
INPUT
COLOR A
INPUT
COLOR
REFERENCE
INPUT
CLOCK
OUTPUT
OSCILLATOR
INPUT
DUTY CYCLE
ADJUST
V
GROUND
CC
RF TANK
LAG
LAG
CHROMA
MODULATOR
B
CHROMA
MODULATOR
A
RF
MODULATOR
RF
OSCILLATOR
CHROMINANCE
OSCILLATOR
and
CLOCK
DRIVER