Radio Shack TRS-80, Service Manual, Page: 19 / 44

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DEVICE SELECTION
SYSTEM TIMING
Figure 5
allows an external device to change the MC-10
memory map. Also, the disable signal for the
memory write is ORed with A12 to prevent a
complete overlap of the 4K of RAM into the 16K
memory map segment.
From the output of the 74LS155 the IY1 output
is used to switch the tri-state controls for the
memory address and data buffers. The IY2 out-
put is ORed with R/W and inverted R/W to pro-
vide a write pulse to the VDG control register
(U8) and a read enable for the keyboard input
buffer. The final output (IY3) is used to select
the ROM chip.
A 74LS155 is used along with four OR gates
and two inverters to provide device selection in
the MC-10. The 74LS155 uses A15 and A14 to
divide the memory map into four 16K seg-
ments. The bottom 16K segment is not used
externally to the CPU. The next 16K segment is
used for system RAM. The third 16K segment is
used to read the keyboard and to write to the
VDG control register. The final 16K is reserved
for system ROM.
Both sections of the LS155 are used so that all
of the device selects may be gated with E, while
the CPU write signal for the RAMs is gated with
window* (U18 pin 6). The disable inputs to the
74LS155 are tied through an inverter to the car-
tridge connector and to a pull-up resistor. This
Internal to the CPU chip, the main clock fre-
quency is divided by 4 to produce the proces-
sor clock E. This clock is used to synchronize
all system operations to the CPU. Figure 5
shows the main clock and timing signals used
in the MC-10. The main clock frequency of 3.579545 MHz is
produced by the oscillator circuit in the modu-
lator. This clock is buffered by one gate of U12
before being connected to the CPU and to the
clock synchronization circuitry.
3.579545 MHz CLK
E CLOCK
AS U1-39
WIN U18-6